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UPD703017AF1 の電気的特性と機能

UPD703017AF1のメーカーはNECです、この部品の機能は「V850/SA1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLER」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD703017AF1
部品説明 V850/SA1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLER
メーカ NEC
ロゴ NEC ロゴ 




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UPD703017AF1 Datasheet, UPD703017AF1 PDF,ピン配置, 機能
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD703014A, 703014AY, 703015A,
703015AY, 703017A, 703017AY
V850/SA1TM
32-/16-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD703014A, 703014AY, 703015A, 703015AY, 703017A, and 703017AY (V850/SA1) are 32-/16-bit single-
chip microcontrollers that include the CPU core of the V850 FamilyTM, and peripheral functions such as ROM/RAM,
timer/counters, serial interfaces, an A/D converter, a timer, and a DMA controller.
In addition to its high real-time responsiveness and one-clock-pitch execution of instructions, the V850/SA1
includes a hardware multiplier for multiplication instructions, saturation instructions, and bit manipulation instructions,
all of which are instructions suited to digital servo control applications. As a real-time control system, this device
provides a high-level cost performance ideal for applications ranging from low-power camcorders and other AV
equipment to portable telephone equipment such as cellular phones and personal handyphone systems (PHS).
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850/SA1 User’s Manual Hardware:
U12768E
V850 FamilyTM User’s Manual Architecture: U10243E
FEATURES
{ Number of instructions: 74
{ Minimum instruction execution time:
59 ns (@ 17 MHz operation with main system clock (fXX))
50 ns (@ 20 MHz operation with main system clock (fXX))
30.5 µs (@ 32.768 kHz operation with subsystem clock (fXT))
{ General-purpose registers: 32 bits × 32 registers
{ Instruction set:
Signed multiplication, saturation operations, 32-bit
shift instructions, bit manipulation instructions,
load/store instructions
{ Memory space:
16 MB linear address space
Memory block allocation function: 2 MB per block
{ External bus interface: 16-bit data bus
Address bus: Separate output enabled
{ Internal memory
Mask ROM: 64 KB (µPD703014A, 703014AY)
128 KB (µPD703015A, 703015AY)
256 KB (µPD703017A, 703017AY)
RAM: 4 KB
(µPD703014A, 703014AY, 703015A, 703015AY)
8 KB (µPD703017A, 703017AY)
{ Interrupts and exception
External: 8, internal: 23, exception: 1
{ I/O lines Total: 85
{ Timer/counters
16-bit timer: 2 channels
8-bit timer: 4 channels
{ Watch timer: 1 channel
{ Watchdog timer: 1 channel
{ Serial interface (SIO)
Asynchronous serial interface (UART)
Clocked serial interface (CSI)
I2C bus interface
(µPD703014AY, 703015AY, 703017AY)
{ A/D converter: 12 channels
{ DMA controller: 3 channels
{ RTP: 8 bits × 1 channel or 4 bits × 2 channels
{ Power-saving functions: HALT/IDLE/STOP modes
{ Packages: 100-pin plastic LQFP (14 × 14)
121-pin plastic FBGA (12 × 12)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14526EJ2V0DS00 (2nd edition)
Date Published September 2000 N CP(K)
Printed in Japan
The mark shows major revised points.
©
2000

1 Page





UPD703017AF1 pdf, ピン配列
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
PIN CONFIGURATION
100-pin plastic LQFP (fine-pitch) (14 × 14)
µPD703014AGC-×××-8EU
µPD703014AYGC-×××-8EU
µPD703015AGC-×××-8EU
µPD703015AYGC-×××-8EU
µPD703017AGC-×××-8EU
µPD703017AYGC-×××-8EU
P21/SO2
P22/SCK2
P23/RXD1
P24/TXD1
P25/ASCK1
VDD
VSS
P26/TI2/TO2
P27/TI3/TO3
P30/TI00
P31/TI01
P32/TI10
P33/TI11
P34/TO0/A13
P35/TO1/A14
P36/TI4/TO4/A15
P37/TI5/TO5
ICNote 1
P100/RTP0/A5
P101/RTP1/A6
P102/RTP2/A7
P103/RTP3/A8
P104/RTP4/A9
P105/RTP5/A10
P106/RTP6/A11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75 P71/ANI1
74 P70/ANI0
73 AVREF
72 AVSS
71 AVDD
70 P65/A21
69 P64/A20
68 P63/A19
67 P62/A18
66 P61/A17
65 P60/A16
64 P57/AD15
63 P56/AD14
62 P55/AD13
61 P54/AD12
60 P53/AD11
59 P52/AD10
58 P51/AD9
57 P50/AD8
56 BVSS
55 BVDD
54 P47/AD7
53 P46/AD6
52 P45/AD5
51 P44/AD4
Notes 1. Connect the IC pin directly to VSS.
2. Applies to the µPD703014AY, 703015AY, and 703017AY only.
Data Sheet U14526EJ2V0DS00
3


3Pages


UPD703017AF1 電子部品, 半導体
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
INTERNAL BLOCK DIAGRAM
NMI
INTP0 to INTP6
TI00, TI01,
TI10, TI11
TO0, TO1
TI2/TO2
TI3/TO3
TI4/TO4
TI5/TO5
SO0
SI0/SDANote 3
SCK0/SCLNote 3
SO1/TXD0
SI1/RXD0
SCK1/ASCK0
SO2
SI2
SCK2
TXD1
RXD1
ASCK1
INTC
Timer/counters
16-bit timer:
TM0, TM1
8-bit timer:
TM2 to TM5
SIO
CSI0/I2CNote 3
CSI1/UART0
CSI2
UART1
DMAC: 3 ch
Watch timer
Watchdog
timer
Mask
ROM
Note 1
RAM
Note 2
CPU
PC
32-bit
barrel shifter
System
registers
General registers
32 bits x 32
Multiplier
16 x 16 32
ALU
Instruction
queue
BCU
HLDRQ (P96)
HLDAK (P95)
ASTB (P94)
DSTB/RD (P93)
R/W/WRH (P92)
UBEN (P91)
LBEN/WRL (P90)
WAIT
A1 to A12
(P100 to P107, P110 to P113)
A13 to A15 (P34 to P36)
A16 to A21 (P60 to P65)
AD0 to AD15
(P40 to P47, P50 to P57)
Port
RTP
A/D
converter
CLKOUT
X1
X2
CG
XT1 (P114)
XT2
RESET
VDD
VSS
BVDD
BVSS
IC
Notes 1. µPD703014A, 703014AY: 64 KB
µPD703015A, 703015AY: 128 KB
µPD703017A, 703017AY: 256 KB
2. µPD703014A, 703014AY, 703015A, 703015AY: 4 KB
µPD703017A, 703017AY: 8 KB
3. Applies to the µPD703014AY, 703015AY, and 703017AY only.
6 Data Sheet U14526EJ2V0DS00

6 Page



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部品番号部品説明メーカ
UPD703017AF1

V850/SA1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLER

NEC
NEC


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