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UPD63210GT の電気的特性と機能

UPD63210GTのメーカーはNECです、この部品の機能は「16-BIT D/A CONVERTER WITH BUILT-IN DIGITAL FILTER FOR AUDIO」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD63210GT
部品説明 16-BIT D/A CONVERTER WITH BUILT-IN DIGITAL FILTER FOR AUDIO
メーカ NEC
ロゴ NEC ロゴ 




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UPD63210GT Datasheet, UPD63210GT PDF,ピン配置, 機能
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD63210,63210L
16-BIT D/A CONVERTER WITH BUILT-IN DIGITAL FILTER FOR AUDIO
DESCRIPTION
The µPD63210 is a 16-bit dual D/A converter IC for digital audio demodulation, which incorporates an 8-times
oversampling digital filter and operational amplifiers for analog post filters. With few external parts and an easy
substrate design (as to 1-bit D/A), it is suitable for multimedia terminals, MPEG audio equipment, video CDs, game
machines, and electronic musical instruments, etc. To cope with sets for portable applications, a low-voltage operating
version µPD63210L (lowest operating supply voltage = +3.0 V) is also available.
FEATURES
• 16-bit resistor string D/A converter (2-channel) adopted
S/N = 104 dBTYP.; DR = 96 dBTYP. (when VDD = 5.0 V)
• High-performance 8-times oversampling digital filter incorporated
Pass band ripple
: ±0.003 dB
Stop band rejection : 90 dB
• System clock 384/512fs selectable
• Serial input data format selectable
Format for 2’S compliment, MSB first, and backward justification data accommodated;
Input can be selected between 16- and 18 bits
• Full line of low-voltage operating products (µPD63210L)
µPD63210 : VDD = 4.5 to 5.5 V
µPD63210L : VDD = 3.0 to 5.5 V
• Wide operating temperature range (TA = –40 to +85 °C)
• Operational amplifier (2-channel) for D/A converter output incorporated
• Operational amplifier (2-channel) for post filter (LPF) configuration incorporated
• Digital de-emphasis function (fs = 32/44.1/48 kHz) incorporated
• Soft mute function incorporated
• CD double-speed playback function (when µPD63210: 384fs)
• 28-pin plastic SOP (375 mil) adopted
ORDERING INFORMATION
Part Number
Package
µPD63210GT
28-pin plastic SOP (375 mil)
µPD63210LGT 28-pin plastic SOP (375 mil)
Quality Grade
Standard
The information in this document is subject to change without notice.
Document No. S11585EJ2V1DS00 (2nd edition)
(Previous No. ID-3466)
Date Published September 1996 P
Printed in Japan
©
1996

1 Page





UPD63210GT pdf, ピン配列
PIN CONFIGURATION (Top View)
TSEL
RST
XTO
XTI
MCKO
CKSEL
BCKI
SDI
LRCKI
DEFS1
DEFS2
DSEL
SMUTE
BSEL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
µPD63210, 63210L
28 DVDD
27 AVDD
26 LO
25 AOL
24 ANIL
23 APIL
22 LREF
21 RREF
20 APIR
19 ANIR
18 AOR
17 RO
16 AGND
15 DGND
TSEL : Test selection input
RST : Reset input
XTO : Oscillation part output pin
XTI : Oscillation part input pin
MCKO : Master clock output
CKSEL : Clock selection input
BCKI : Bit clock input
SDI : Serial data input
LRCKI : LR clock input
DEFS1 : De-emphasis select input 1
DEFS2 : De-emphasis select input 2
DSEL : Double-speed playback select input
SMUTE : Soft mute control input
BSEL : Data bit count select input
DGND : Digital ground
AGND : Analog ground
RO : D/A converter output (R channel)
AOR : Filter amplifier output (R channel)
ANIR : Filter amplifier inverting input (R channel)
APIR : Filter amplifier non-inverting input (R channel)
RREF : Reference (R channel)
LREF : Reference (L channel)
APIL : Filter amplifier non-inverting input (L channel)
ANIL : Filter amplifier inverting input (L channel)
AOL : Filter amplifier output (L channel)
LO : D/A converter output (L channel)
AVDD : Analog power supply
DVDD : Digital power supply
3


3Pages


UPD63210GT 電子部品, 半導体
µPD63210, 63210L
AC Characteristics (µPD63210: DVDD = AVDD = 4.5 to 5.5 V, DGND = AGND = 0 V, Ta = –40 to +85 °C unless
otherwise specified)
(µPD63210L: DVDD = AVDD = 3.0 to 5.5 V, DGND = AGND = 0 V, Ta = –40 to +85 °C unless
otherwise specified)
Parameter
Oscillator frequency
Master clock frequency
Master clock pulse width
(“H” section)
Master clock pulse width
(“L” section)
BCK pulse width
(“H” section)
BCK pulse width
(“L” section)
BCK pulse cycle
Data setup time
Data hold time
LRCK setup time
LRCK hold time
SMUTE pulse width
(“H” section)
Symbol
fX
fMCK
tMWH
tMWL
tBWH
tBWL
tBW
tDS
tDH
tLRS
tLRH
tSMWH
Condition
Crystal oscillation: 384fs;
512fs
External clock input: 384fs;
512fs
External clock input: 384fs;
512fs
External clock input: 384fs;
512fs
MIN.
10
10
10
10
25
19
25
19
150
TYP.
16.9344
22.5792
16.9344
22.5792
MAX.
19.2
25.6
19.2
25.6
150
310
100
100
100
100
8/fs
Unit
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XTI
tMWH
tMWL
VIH
VIL
BCKI
SDI
LRCKI
tBWH
tBW
tBWL
tDS tDH
tLRH
tLRS
VIH
0.5 * DVDD
VIL
0.5 * DVDD
0.5 * DVDD
6

6 Page



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共有リンク

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部品番号部品説明メーカ
UPD63210GT

16-BIT D/A CONVERTER WITH BUILT-IN DIGITAL FILTER FOR AUDIO

NEC
NEC


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