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UPD6124ACS の電気的特性と機能

UPD6124ACSのメーカーはNECです、この部品の機能は「4-BIT SINGLE-CHIP MICROCONTROLLER FOR REMOTE CONTROL TRANSMISSION」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD6124ACS
部品説明 4-BIT SINGLE-CHIP MICROCONTROLLER FOR REMOTE CONTROL TRANSMISSION
メーカ NEC
ロゴ NEC ロゴ 




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UPD6124ACS Datasheet, UPD6124ACS PDF,ピン配置, 機能
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD6124A, 6600A
4-BIT SINGLE-CHIP MICROCONTROLLER
FOR REMOTE CONTROL TRANSMISSION
DESCRIPTION
The µPD6124A and 6600A are 4-bit single-chip microcontrollers for infrared remote controllers for TVs, VCRs,
stereos, cassette decks, air conditions, etc.
These microcontrollers consist of ROM, RAM, a 4-bit parallel-processing ALU, a programmable timer, key input/
output ports, and transmit output ports. Functioning is controlled by a program.
A one-time PROM, model µPD61P24, to which a program can be written only once is also available. This one-time
PROM is ideal for evaluation of programs running in a µPD6124A or 6600A, and for small-scale production of such
systems.
FEATURES
Transmitter for programmable infrared remote control-
ler
19 types of instructions
Instruction execution time: 17.6 µs (with 455-kHz ce-
ramic resonator)
Program memory (ROM) capacity
µPD6124A: 1002 × 10 bits
µPD6600A: 512 × 10 bits
Data memory (RAM) capacity: 32 × 5 bits
9-bit programmable timer: 1 channel
I/O pins (KI/O): 8 pins
Input pins (KI): 4 pins
Serial input pins (S-IN): 1 pin
Transmission-in-progress indication pin (S-OUT): 1
pin
Transmit carrier frequency (REM)
fOSC/12, fOSC/8
Standby operation (HALT/STOP mode)
Low power consumption
Current consumption in STOP mode (TA = 25°C)
Low-voltage operation
µPD6124A: VDD = 2.2 to 5.5 V
µPD6600A: VDD = 2.2 to 3.6 V
Caution To use the NEC transmission format, ask NEC to supply the custom code.
Do not use R0 when using a register as an operand of the branch instruction.
The information in this document is subject to change without notice.
Document No. U12391EJ5V0DS00 (5th edition)
(Previous No. IC-1927)
Date Published June 1997 N
Printed in Japan
The mark shows major revised points.
© 1989

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UPD6124ACS pdf, ピン配列
µPD6124A, 6600A
BLOCK DIAGRAM
ROM
D.P.
ROM
D.P.
L
H
PC(L)
PC(H)
Note
ROM
M (L)
P
X
ROM
(H)
SP
ADD
DEC
32 ×5 bits
CNTL CNTL
(L) (H)
M RAM
P
X RAM
OSC
TIMER TIMER
(L) (H)
10 bits
MOD
ALU
ACC
KEY KEY
OUT(L) OUT(H)
KEY
IN
To S-OUT
Watchdog Low-
timer
function
voltage
detector
circuit
OSC-IN S-OUT REM
OSC-OUT
Note ROM capacity depends on the products.
S-IN
KI/O0-KI/O7
K I0-KI3
AC
DIFFERENCES AMONG PRODUCTS
Item Product Name
µPD6124A
ROM Capacity
1002 × 10 bits (Mark ROM)
RAM Capacity
32 × 5 bits
I/O Pins
8 (KI/O0-KI/O7)
S-IN Pins
Provided
Current Consumption
2 µA
(fOSC = STOP) (MAX.)
S-IN High Level Input
30 µA
Current (MAX.)
Transmit Carrier Frequency fOSC/12, fOSC/8
Low-voltage Detector
Provided
(Reset) Circuit
Supply Current
VDD = 2.2 to 5.5 V
Package
• 20-pin plastic SOP (300 mil)
• 20-pin plastic shrink DIP (300 mil)
µPD6600A
512 × 10 bits (Mask ROM)
VDD = 2.2 to 3.6 V
3


3Pages


UPD6124ACS 電子部品, 半導体
µPD6124A, 6600A
5. DATA POINTER (R0)
R0 (R10, R00) for the data memory can serve as the data pointer for the ROM.
R0 specifies the low-order 8 bits in the ROM address. The high-order 2 bits in the ROM address are specified by
the control register.
Table referencing for ROM data can be easily executed by calling the ROM contents by setting the ROM address
to the data pointer.
On reset or “all clear” is input, it becomes undefined.
Figure 5-1. Data Pointer Organization
Control registers
(P1 )
AD9Note AD 8
R10 R00
AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0 R 0
Note µPD6600A: AD9 = 0
6. ACCUMULATOR (A) ……… 4 BITS
The accumulator (A) is a 4-bit register. The accumulator plays a major role in each operation.
On reset or “all clear” is input, it becomes undefined.
Figure 6-1. Accumulator Organization
A3 A2
A1 A0
A
7. ARITHMETIC LOGIC UNIT (ALU) ……… 4 BITS
The arithmetic logic unit (ALU) is a 4-bit operation circuit, and executes simple operations, such as arithmetic
operations.
8. FLAGS
(1) Status flag
When the status for each pin is checked by the STTS instruction, if the condition coincides with the condition
specified by the STTS instruction, the status flag (F) is set (to 1).
On reset or “all clear” is input, it becomes undefined.
(2) Carry flag
When the INC (increment) instruction or the RL (rotate left) instruction is executed, if a carry is generated from
the MSB for the accumulator, the carry flag (C) is set (to 1).
The carry flag (C) is also set (to 1), if the contents for the accumulator are “FH”, when the SCAF instruction
is executed.
On reset or “all clear” is input, it becomes undefined.
6

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部品番号部品説明メーカ
UPD6124ACS

4-BIT SINGLE-CHIP MICROCONTROLLER FOR REMOTE CONTROL TRANSMISSION

NEC
NEC


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