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PDF UPD4564323 Data sheet ( Hoja de datos )
| Número de pieza | UPD4564323 | |
| Descripción | 64M-bit Synchronous DRAM 4-bank/ LVTTL | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4564323 for Rev. E
64M-bit Synchronous DRAM
4-bank, LVTTL
Description
The µPD4564323 is a high-speed 67,108,864-bit synchronous dynamic random-access memory, organized as
524,288 words × 32 bits × 4 banks.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 86-pin TSOP (II).
Features
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• ×32 organization
• Byte control by DQM0, DQM1, DQM2 and DQM3
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable /CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• Single 3.3 V ± 0.3 V power supply
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64 ms
• Burst termination by Burst stop command and Precharge command
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14376EJ2V0DS00 (2nd edition)
Date Published December 1999 NS CP (K)
Printed in Japan
The mark • shows major revised points.
©
1999
1 page  
Block Diagram
CLK
CKE
Clock
Generator
Address
Mode
Register
/CS
/RAS
/CAS
/WE
Row
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Burst
Counter
µPD4564323 for Rev. E
Bank D
Bank C
Bank B
Bank A
Sense Amplifier
Column Decoder &
Latch Circuit
Data Control Circuit
DQM
DQ
Data Sheet M14376EJ2V0DS00
5
5 Page 
µPD4564323 for Rev. E
Self refresh entry command
Fig.7 Self refresh entry command
(/CS, /RAS, /CAS, CKE = Low, /WE = High)
After the command execution, self refresh operation continues while CKE
remains low. When CKE goes high, the µPD4564323 exits the self refresh
mode.
During self refresh mode, refresh interval and refresh operation are
performed internally, so there is no need for external control.
Before executing self refresh, all banks must be precharged.
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0, BA1
(Bank select)
A10
Add
Burst stop command
(/CS, /WE = Low, /RAS, /CAS = High)
This command can stop the current burst operation.
Fig.8 Burst stop command in Full
Page Mode
CLK
CKE H
/CS
/RAS
/CAS
/WE
BA0, BA1
(Bank select)
A10
Add
No operation
(/CS = Low, /RAS, /CAS, /WE = High)
This command is not an execution command. No operations begin or
terminate by this command.
Fig.9 No operation
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0, BA1
(Bank select)
A10
Add
H
Data Sheet M14376EJ2V0DS00
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet UPD4564323.PDF ] | |
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