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UPD45128441G5-A75のメーカーはNECです、この部品の機能は「128M-bit Synchronous DRAM 4-bank/ LVTTL」です。 |
部品番号 | UPD45128441G5-A75 |
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部品説明 | 128M-bit Synchronous DRAM 4-bank/ LVTTL | ||
メーカ | NEC | ||
ロゴ | |||
このページの下部にプレビューとUPD45128441G5-A75ダウンロード(pdfファイル)リンクがあります。 Total 70 pages
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD45128441, 45128841, 45128163
128M-bit Synchronous DRAM
4-bank, LVTTL
Description
The µPD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access
memories, organized as 8,388,608 × 4 × 4, 4,194,304 × 8 × 4, 2,097,152 × 16 × 4 (word × bit × bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 54-pin TSOP (II).
Features
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0(A13) and BA1(A12)
• Byte control (×16) by LDQM and UDQM
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable /CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• ×4, ×8, ×16 organization
• Single 3.3 V ± 0.3 V power supply
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64 ms
• Burst termination by Burst stop command and Precharge command
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M12650EJBV0DS00 (11th edition)
Date Published April 2000 NS CP (K)
Printed in Japan
The mark • shows major revised points.
©
1997
1 Page µPD45128441, 45128841, 45128163
Part Number
[ x4, x8 ]
µPD45128841G5 - A75
NEC Memory
Synchronous DRAM
Memory density
128 : 128M bits
Organization
4 : x4
8 : x8
Minimum cycle time
75 : 7.5 ns (133 MHz)
80 : 8 ns (125 MHz)
10 : 10 ns (100 MHz)
10B: 10 ns (100 MHz)
Number of banks
4 : 4 banks
Interface
1 : LVTTL
[ x16 ]
163
Low voltage
A : 3.3 V ± 0.3 V
Package
G5 : TSOP (II)
Organization
16 : x16
Number of banks
and Interface
3 : 4 banks, LVTTL
Data Sheet M12650EJBV0DS00
3
3Pages µPD45128441, 45128841, 45128163
[µPD45128163]
54-pin Plastic TSOP (II) (10.16mm (400))
2M words × 16 bits × 4 banks
VCC
DQ0
VCCQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VCCQ
DQ5
DQ6
VSSQ
DQ7
VCC
LDQM
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 Vss
53 DQ15
52 VssQ
51 DQ14
50 DQ13
49 VccQ
48 DQ12
47 DQ11
46 VssQ
45 DQ10
44 DQ9
43 VccQ
42 DQ8
41 Vss
40 NC
39 UDQM
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 Vss
A0 to A11 Note
: Address inputs
BA0(A13), BA1(A12): Bank select
DQ0 to DQ15
: Data inputs / outputs
CLK : Clock input
CKE
: Clock enable
/CS : Chip select
/RAS
: Row address strobe
/CAS
: Column address strobe
/WE : Write enable
LDQM
: Lower DQ mask enable
UDQM
: Upper DQ mask enable
VCC : Supply voltage
VSS : Ground
VCCQ
: Supply voltage for DQ
VSSQ
: Ground for DQ
NC : No connection
Note A0 to A11 : Row address inputs
A0 to A8 : Column address inputs
6 Data Sheet M12650EJBV0DS00
6 Page | |||
ページ | 合計 : 70 ページ | ||
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PDF ダウンロード | [ UPD45128441G5-A75 データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
UPD45128441G5-A75 | 128M-bit Synchronous DRAM 4-bank/ LVTTL | NEC |
UPD45128441G5-A75-9JF | 128M-bit Synchronous DRAM 4-bank/ LVTTL | NEC |