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UPD2845GRのメーカーはNECです、この部品の機能は「1 V/ 1.3 mA/ 94MHz PLL SYNTHESIZER LSI FOR PAGER SYSTEM」です。 |
部品番号 | UPD2845GR |
| |
部品説明 | 1 V/ 1.3 mA/ 94MHz PLL SYNTHESIZER LSI FOR PAGER SYSTEM | ||
メーカ | NEC | ||
ロゴ | |||
このページの下部にプレビューとUPD2845GRダウンロード(pdfファイル)リンクがあります。 Total 16 pages
DDAATTAA SSHHEEEETT
CMOS DIGITAL INTEGRATED CIRCUITS
PPD2845GR
1 V, 1.3 mA, 94MHz PLL SYNTHESIZER LSI
FOR PAGER SYSTEM
DESCRIPTION
PPD2845GR is a PLL synthesizer LSI for pager system. This LSI is manufactured using low voltage CMOS
process and therefore realized the low power consumption PLL operated on 1 V, 1.3 mA. This LSI is packaged in 16
pin plastic SSOP suitable for high-density surface mounting. So, this product contributes to produce a long-life-
battery and physically-small pager system.
FEATURES
• Operating frequency : · Input frequency : fin = 10 MHz to 94 MHz
· Reference oscillating frequency : fx’tal = 12.8 MHz
• Low Supply voltage : · PLL block : VDD1 = 1.00 V to 1.15 V @ fin = 10 MHz to 70 MHz
VDD1 = 1.05 V to 1.15 V @ fin = 10 MHz to 94 MHz
· Charge pump block: VDD2 = 3.0 V ± 300 mV
• Low power consumption • IDD = 1.3 mA TYP. @ fin = 70 MHz, fx’tal = 12.8 MHz
• Equipped with power-save function • Serial data can be received in power-save mode.
• Packaged in 16 pin plastic SSOP suitable for high-density surface mounting.
ORDERING INFORMATION
PART NUMBER
PPD2845GR-E1
PPD2845GR-E2
PACKAGE
16 pin plastic SSOP
(225 mil)
16 pin plastic SSOP
(225 mil)
SUPPLYING FORM
Embossed tape 12 mm wide. QTY 2.5 k/reel
Pin 1 is in tape pull-out direction.
Embossed tape 12 mm wide. QTY 2.5 k/reel
Pin 1 is in tape roll-in direction.
* To order evaluation samples, please contact your local NEC sales office (Order number : PPD2845GR).
PIN ASSIGNMENT
(Top View)
VDD1
XI
FIN XO
GND
LE
FR CLK
RESET
DATA
EO PS
EOP
NC
EON
VDD2
Caution Electro-static sensitive devices
Document No. P12150EJ2V0DS00 (2nd edition)
(Previous No. IC-3291)
Date Published February 1997 N
Pi di J
© 1994
1 Page PPD2845GR
PIN EXPLANATION
PIN No.
1
2
3
4
PIN NAME
VDD1
FIN
GND
FR
5 RESET
6 EO
7 EOP
8 EON
9 VDD2
10 NC
11 PS
12 DATA
13 CLK
14 LE
15 XO
16 XI
I/O EXPLANATION FOR FUNCTION
• Supply voltage to PLL block
I Frequency Input
• Ground
O Test pin for monitor.
Normally used as PLL, output L should be selected by test bit and this pin should be
opened. (Refer to setting for reference counter on 11 page)
I Test pin for monitor reset. (Refer to RESET on 12 page)
Normally used as PLL, this pin should be grounded.
O Internal charge pump output. In the case of passive filter, this output should be used.
Input signal phase fp vs. reference signal fr
fp > fr : Low output
fp < fr : High output
fp = fr : High-impedance
Outputs for external charge pump. In the case of active filter, this outputs should be used.
O EOP : PCH open drain
O EON : NCH open drain
EON
EOP
• Supply voltage to charge pump.
• Non Connection.
I Control bias input for power-save (Refer to Power-save on 12 page).
I Data input for divided ratio.
I Clock input for shift register.
I Latch enable input.
O X’tal oscillator connection pin.
I
3
3Pages PPD2845GR
TEST CIRCUIT
DC measurement
BS2
2
GND
4
5
6
7
8
VDD1
XI
FIN XO
GND
LE
FR CLK
RESET DATA
EO PS
EOP
NC
EON
VDD2
µPD2845GR
relay RL1
C1
X’tal
D1
BS3
C2
GND
16
15
14
13
12
11
10
BS1
relay RL1
Diode D1
Capacitor C1,C2
X’tal
: SRR-204
: 1S945
: 18 pF
: 12.8 MHz
AC measurement
VDD1
VDD2
1µF
1µF 50 Ω
BNC1
BNC2
SW 1
100 pF
1 000 pF
SW3
VDD1
XI
FIN XO
GND
LE
FR CLK
RESET
DATA
EO PS
EOP
NC
EON
VDD2
µPD2845GR
10 pF
X’tal 12.8 MHz
10 pF
SW2
BNC1 : Frequency input
BNC2 : Frequency output
SW1 : switch for voltage on/off
SW2 : Desired for PS mode : Low
SW3 : Desired for reset mode : High
100 pF
6
6 Page | |||
ページ | 合計 : 16 ページ | ||
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PDF ダウンロード | [ UPD2845GR データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
UPD2845GR | 1 V/ 1.3 mA/ 94MHz PLL SYNTHESIZER LSI FOR PAGER SYSTEM | NEC |