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UPD17P719GC-3B9 の電気的特性と機能

UPD17P719GC-3B9のメーカーはNECです、この部品の機能は「4-BIT SINGLE-CHIP MICROCONTROLLER WITH BUILT-IN HARDWARE DEDICATED TO DIGITAL TUNING SYSTEMS」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD17P719GC-3B9
部品説明 4-BIT SINGLE-CHIP MICROCONTROLLER WITH BUILT-IN HARDWARE DEDICATED TO DIGITAL TUNING SYSTEMS
メーカ NEC
ロゴ NEC ロゴ 




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UPD17P719GC-3B9 Datasheet, UPD17P719GC-3B9 PDF,ピン配置, 機能
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD17P719
4-BIT SINGLE-CHIP MICROCONTROLLER WITH
BUILT-IN HARDWARE DEDICATED TO DIGITAL TUNING SYSTEMS
The µPD17P719 is produced by replacing the built-in masked ROM of the µPD17717, µPD17718, and µPD17719
with a one-time PROM.
The µPD17P719 allows programs to be written once, so that the µPD17P719 is suitable for preproduction in
µPD17717, µPD17718, or µPD17719 system development or low-volume production.
When reading this document, also refer to the publications on the µPD17717, µPD17718, or µPD17719.
The electrical characteristics (including power supply currents) and PLL analog characteristics of
the µPD17P719 differ from those of the µPD17717, µPD17718, and µPD17719. In high-volume application
set production, carefully check those differences.
FEATURES
Compatible with the µPD17717, µPD17718, and µPD17719
Built-in one-time PROM : 32K bytes (16384 × 16 bits)
Supply voltage
: PLL operation : VDD = 4.5 to 5.5 V
CPU operation : VDD = 3.5 to 5.5 V
ORDERING INFORMATION
Part number
µPD17P719GC-3B9
Package
80-pin plastic QFP (14 × 14 mm, 0.65-mm pitch)
The information in this document is subject to change without notice.
Document No. U12112EJ1V0DS00 (1st edition)
Date Published February 1997 J
Printed in Japan
© 1997

1 Page





UPD17P719GC-3B9 pdf, ピン配列
µPD17P719
(2/2)
Item
BEEP output
Reset
Standby
Product
µPD17717
µPD17718
µPD17719
µPD17P719
2
Output frequency : 1 kHz, 3 kHz, 4 kHz, 6.7 kHz (BEEP0 pin)
67 Hz, 200 Hz, 3 kHz, 4 kHz (BEEP1 pin)
• Power-on reset (when the power is turned on)
• Reset using the RESET pin
• Watchdog timer reset
Can be set only once at power-on: 65,536 instructions, 131,072 instructions, or non-use
can be selected.
• Stack pointer overflow/underflow reset
Can be set only once at power-on: the interrupt stack or address stack can be selected.
• CE reset (CE pin: low high)
A CE reset delay timing can be set.
• Power-failure detection function
• Clock stop mode (STOP)
• Halt mode (HALT)
Supply voltage
Package
• PLL operation : VDD = 4.5 to 5.5 V
• CPU operation : VDD = 3.5 to 5.5 V
80-pin plastic QFP (14 × 14 mm, 0.65-mm pitch)
3


3Pages


UPD17P719GC-3B9 電子部品, 半導体
PIN NAMES
AD0-AD5
: A/D converter inputs
AMIFC
: AM frequency counter input
ASCK
: UART serial clock I/O
BEEP0, BEEP1 : Beep outputs
CE : Chip enable
CLK : Address update clock input
D0-D7
: Data I/O
EO0, EO1
: Error outputs
FCG0, FCG1 : Frequency counter gate inputs
FMIFC
: FM frequency counter input
GND0-GND2 : Ground 0 to 2
INT0-INT4
: External interrupt inputs
MD0-MD3
: Operating mode selection
PWM0-PWM2 : D/A converter outputs
P0A0-P0A3 : Port 0A
P0B0-P0B3 : Port 0B
P0C0-P0C3 : Port 0C
P0D0-P0D3 : Port 0D
P1A0-P1A3 : Port 1A
P1B0-P1B3 : Port 1B
P1C0-P1C3 : Port 1C
P1D0-P1D3 : Port 1D
P2A0-P2A2 : Port 2A
P2B0-P2B3 : Port 2B
µPD17P719
P2C0-P2C3 : Port 2C
P2D0-P2D2 : Port 2D
P3A0-P3A3 : Port 3A
P3B0-P3B3 : Port 3B
P3C0-P3C3 : Port 3C
P3D0-P3D3 : Port 3D
REG
: CPU regulator
RESET
: Reset input
RxD : UART serial data input
SB0, SB1 : SBI serial data I/O
SCK
: SBI serial clock I/O
SCK2, SCK3 : 3-wire serial clock I/O
SCL : 2-wire serial clock I/O
SDA
: 2-wire serial data I/O
SI2, SI3
: 3-wire serial data input
SO2, SO3 : 3-wire serial data output
TEST
: Test input
TM0G
: Timer 0 gate input
TxD : UART serial data output
VCOH
: Local oscillation high input
VCOL
: Local oscillation low input
VDD0, VDD1 : Power supply
VPP : Program voltage application
XIN, XOUT
: Main clock oscillation
6

6 Page



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共有リンク

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部品番号部品説明メーカ
UPD17P719GC-3B9

4-BIT SINGLE-CHIP MICROCONTROLLER WITH BUILT-IN HARDWARE DEDICATED TO DIGITAL TUNING SYSTEMS

NEC
NEC


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