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PDF UPD178F098 Data sheet ( Hoja de datos )
| Número de pieza | UPD178F098 | |
| Descripción | 8-BIT SINGLE-CHIP MICROCONTROLLER | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD178F098
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD178F098 is a flash memory model of the µPD178076, 178078, 178096, and 178098, and is provided with
a flash memory to/from which data can be written/erased with the microcontroller mounted on a printed circuit board.
For the detailed functional description, refer to the following User’s Manuals:
µPD178078, 178098 Subseries User’s Manual: U12790E
78K/0 Series User’s Manual - Instruction : U12326E
FEATURES
• Serial interface (UART mode)
• IEBusTM controller
• Pin-compatible with mask ROM models (except VPP pin)
• Flash memory: 60K bytesNote
• Internal high-speed RAM: 1024 bytes
• Internal extension RAM: 2048 bytesNote
• Buffer RAM: 32 bytes
• Operable at same supply voltage as mask ROM models (VDD = 4.5 to 5.5 V during PLL operation)
Note The capacities of the flash memory and internal extension RAM can be changed using the memory size
select register (IMS) and internal extension RAM size select register (IXS).
Remark For the differences between the flash memory model and mask ROM models, refer to 1. DIFFERENCES
BETWEEN µPD178F098 AND MASK ROM MODELS.
The electrical specifications (such as supply current) in the µPD178F098 differ from those of the
mask ROM models. Confirm these differences before mass-producing any application set.
APPLICATION FIELD
Car stereos
ORDERING INFORMATION
Part Number
µPD178F098GF-3BA
Package
100-pin plastic QFP (14 × 20)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. U12920EJ1V0DS00
Date Published June 2000 N CP(K)
Printed in Japan
The mark shows major revised points.
©
1997, 2000
1 page  
PIN CONFIGURATION (Top View)
• 100-pin plastic QFP (14 × 20)
µPD178F098GF-3BA
µPD178F098
P00/INTP0
P01/INTP1
P20/SI1
P21/SO1
P22/SCK1
P23/STB
P24/BUSY
P25/SI0/SB0/SDA0
P26/SO0/SB1/SDA1
P27/SCK0/SCL
P70/SI3
P71/SO3
P72/SCK3
P73
P50
P51
P52
P53
P54
P55
P56
P57
P10/ANI0
P11/ANI1
P12/ANI2
P13/ANI3
AVDD
P14/ANI4
P15/ANI5
P16/ANI6
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P06/INTP6
P05/INTP5
P04/INTP4
P124
P123
P122
P121/RX0
P120/TX0
P77
P76
P75/TXD0
P74/RXD0
P137
P136
P135
P134
P133
P132
P131/TO51
P130/TO50
P37/BUZ
P36/BEEP0
P35/TI51
P34/TI50
P33/TI01
P32/TI00
P31/TO0
P30/VM45
P03/INTP3
P02/INTP2
Cautions 1. Directly connect the VPP pin to GND0, GND1, or GND2 in normal operating mode.
2. Keep the voltage at AVDD, VDDPORT, and VDDPLL same as that at the VDD pin.
3. Keep the voltage at AVSS, GNDPORT, and GNDPLL same as that at GND0, GND1, or GND2.
4. Connect each of the REGOSC and REGCPU pins to GND via a 0.1-µF capacitor.
Data Sheet U12920EJ1V0DS00
5
5 Page 
µPD178F098
2.1 Port Pins (2/2)
Pin Name
P100
P101
P102
P120
P121
P122-P124
P130
P131
P132-P137
I/O
I/O
I/O
Output
Function
Port 10.
3-bit I/O port.
Can be set in input or output mode in 1-bit units.
Port 12.
5-bit I/O port.
Can be set in input or output mode in 1-bit units.
Port 13.
8-bit output port.
N-ch open-drain output port (15 V withstand)
At Reset
Input
Input
Low-level
output
Shared by:
–
AMIFC
FMIFC
TX0
RX0
–
TO50
TO51
–
2.2 Pins Other Than Port Pins (1/2)
Pin Name
I/O
INTP0-INTP7 Input
SI0
SI1
SI3
SO0
SO1
SO3
SB0
SB1
SDA0
SDA1
SCK0
SCK1
SCK3
SCL
STB
BUSY
VW45
TI00
TI01
TI50
TI51
TO0
TO50
TO51
BEEP0
BUZ
Input
Output
I/O
I/O
Output
Input
Output
Input
Input
Output
Output
Function
External maskable interrupt input whose valid edge
(rising edge, falling edge, or both rising and falling edges)
can be specified.
Serial data input to serial interface.
Serial data output from serial interface.
Serial data input/output to/from
serial interface.
N-ch open drain I/O
Serial clock input/output to/from serial interface.
N-ch open drain I/O
Strobe output for serial interface automatic transmission/
reception.
Busy input for serial interface automatic transmission/
reception.
VDD = 4.5 V monitor output
External count clock input to 16-bit timer (TM0).
External count clock input to 8-bit timer (TM50).
External count clock input to 8-bit timer (TM51).
16-bit timer (TM0) output.
8-bit timer (TM50) output.
8-bit timer (TM51) output.
Buzzer output.
At Reset
Input
Shared by:
P00-P07
Input
Input
Input
Input
Input
P25/SB0/SDA0
P20
P70
P26/SB1/SDA1
P21
P71
P25/SI0/SDA0
P26/SO0/SDA1
P25/SI0/SB0
P26/SO0/SB1
P27/SCL
P22
P72
P27/SCK0
P23
Input
P24
Input
Input
Input
Input
Low-level
output
Input
P30
P32
P33
P34
P35
P31
P130
P131
P36
P37
Data Sheet U12920EJ1V0DS00
11
11 Page | ||
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| PDF Descargar | [ Datasheet UPD178F098.PDF ] | |
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