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PDF UPD178003 Data sheet ( Hoja de datos )
| Número de pieza | UPD178003 | |
| Descripción | 8-BIT SINGLE-CHIP MICROCONTROLLERS | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD178002, 178003
8-BIT SINGLE-CHIP MICROCONTROLLERS
The µPD178002 and 178003 are 8-bit single-chip CMOS microcontrollers that incorporate hardware for digital
tuning systems.
The CPU uses the 78K/0 architecture, which makes it easy to implement high-speed access to internal memory
and control of peripheral hardware. Also, the instructions used are the high-speed 78K/0 instructions, suitable for
system control.
The peripheral hardware includes an input/output port, 8-bit timer, A/D converter, serial interface, power-on-clear
circuits, as well as a pre-scaler for digital tuning, a PLL frequency synthesizer, and a frequency counter.
The µPD178P018A, one-time PROM or EPROM versions that can be operated in the same supply voltage range
as for the mask ROM versions, and various development tools, are also available.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µPD178003 Subseries User’s Manual:
U13033E
78K/0 Series User’s Manual — Instructions: U12326E
FEATURES
• Program memory (ROM) capacity
µPD178002: 16 Kbytes
µPD178003: 24 Kbytes
• Data memory (RAM) capacity: 512 bytes
• Instruction cycle: 0.44 µs (4.5 MHz crystal resonator used)
• Selected peripheral hardware of the µPD178018A Subseries
General-purpose I/O ports, A/D converter, serial interface, timer, frequency counter, power-on-clear circuits.
• On-chip hardware for a PLL frequency synthesizer.
Dual modulus pre-scaler, programmable divider, phase comparator, charge pump.
• Vector interrupt sources: 8
• Supply Voltage: VDD = 4.5 to 5.5 V (during PLL operation)
VDD = 3.5 to 5.5 V (during CPU operation, when the system clock is fX/2 or lower)
VDD = 4.5 to 5.5 V (during CPU operation, when the system clock is fX)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U12628EJ3V0DS00 (3rd edition)
Date Published December 1999 N CP(K)
Printed in Japan
The mark shows major revised points.
©
1997, 1999
1 page  
1. PIN CONFIGURATION (TOP VIEW)
• 80-PIN PLASTIC QFP (14 × 14 mm, 0.65 mm pitch)
µPD178002GC-×××-3B9
µPD178003GC-×××-3B9
µPD178002, 178003
P10/ANI0
P11/ANI1
P12/ANI2
P13
P14
P15
P20/SI1
P21/SO1
P22/SCK1
P23
P24
P25
P26
P27
P132
P133
P134
P40
P41
P42
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1 60
2 59
3 58
4 57
5 56
6 55
7 54
8 53
9 52
10 51
11 50
12 49
13 48
14 47
15 46
16 45
17 44
18 43
19 42
20 41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P37
P36/BEEP
P35
P34/TI2
P33/TI1
P32
P31
P30
P67
P66
P65
P64
P63
P62
P61
P60
P57
P56
P55
P54
Cautions 1. Connect the IC (Internally Connected) pin directly to GND.
2. Connect VDDPORT and VDDPLL pins to VDD.
3. Connect the GNDPORT and GNDPLL pins to GND.
4. Connect each of the REGOSC and REGCPU pins to GND via a 0.1 µF capacitor.
Data Sheet U12628EJ3V0DS00
5
5 Page 
µPD178002, 178003
Type 2
Figure 3-1. Pin Input/Output Circuits (1/2)
Type 8
IN
Schmitt-triggered input with
hysteresis characteristics
Data
Output
disable
VDD
P-ch
N-ch
IN/OUT
Type 5
Data
Output
disable
Input
enable
VDD
P-ch
N-ch
Type 10
Data
IN/OUT
Open drain
Output disable
VDD
P-ch
N-ch
IN/OUT
Type 5-G
Data
Output
disable
VDD
P-ch
N-ch
Type 11-A
Data
VDD
P-ch
IN/OUT
Output
disable
Comparator
+_
P-ch
N-ch
N-ch
VREF (Threshold voltage)
Input
enable
IN/OUT
Remark All VDD and GND in the above figures are the positive power supply and ground potential of the ports,
and should be read as VDDPORT and GNDPORT, respectively.
Data Sheet U12628EJ3V0DS00
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet UPD178003.PDF ] | |
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