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UPD16879 の電気的特性と機能

UPD16879のメーカーはNECです、この部品の機能は「MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD16879
部品説明 MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT
メーカ NEC
ロゴ NEC ロゴ 




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UPD16879 Datasheet, UPD16879 PDF,ピン配置, 機能
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16879
MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT
The µPD16879 is a monolithic quad H bridge driver IC that employs a CMOS control circuit and a MOSFET output
circuit. Because it uses MOSFETs in its output stage, this driver IC consumes less power than conventional driver
ICs that use bipolar transistors.
Because the µPD16879 controls a motor by inputting serial data, its package has been shrunk and the number of
pins reduced. As a result, the performance of the application set can be improved and the size of the set has been
reduced.
This IC employs a current-controlled 64-step micro step driving method that drives stepper motor with low
vibration.
The µPD16879 is a housed in a 38-pin shrink SOP to contribute to the miniaturization of application set.
This IC can simultaneously drive two stepper motors and is ideal for the mechanisms of camcorders.
FEATURES
Four H bridge circuits employing power MOS FETs
Current-controlled 64-step micro step driving
Motor control by serial data (8 bits × 13 bytes)
PWM-frequency, output current and number of output pulse can be setting by serial data.
3-V power supply.
Minimum operating voltage: 2.7 V
Low consumption current.
VDD pin current (operating mode) : 3 mA (MAX.)
Power save circuit bult in.
VDD pin current (power save mode) : 100 µA (MAX.) fCLK: OFF state
VDD pin current (power save mode) : 300 µA (MAX.) fCLK: 4.5 MHz input
38-pin shrink SOP (7.62 mm (300))
ORDERING INFORMATION
Part Number
Package
µPD16879GS-BGG
38-pin plastic shrink SOP (7.62 mm (300))
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14188EJ1V0DS00 (1st edition)
Date Published July 2000 N CP(K)
Printed in Japan
©
2000

1 Page





UPD16879 pdf, ピン配列
µPD16879
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, TA = 25°C, VDD = 3 V, VM = 5.4 V, fCLK = 4.5 MHz, COSC = 68 pF, CFIL = 1000 pF,
VREF = 250 mV, EVR = 100 mV (10000))
Parameter
Symbol
Conditions
MIN. TYP. MAX. Unit
Off state VM pin current
IMO(RESET) No load, Reset period
1.0 µA
Operating state VDD pin current
IDD
VDD pin current
IDD(RESET)
Power save state VDD pin current IDD(PS)1
IDD(PS)2
Output open
Reset period
tCLK = off
fCLK = 4.5 MHZ
3.0 mA
100 µA
100 µA
300 µA
High level input voltage
Low level input voltage
VIH LATCH, SCLK, SDATA, VD, VD
VIL RESET, OSCIN, VREFsel
0.7 × VDD
0.3 × VDD
V
V
Input hysteresis vosltage
VH
0.3 V
Monitor output voltage 1
(EXTOUT α, β)
VOMα(H)
VOMβ(H)
VOMα(L)
VOMβ(L)
Monitor output voltage 2
(EXP 0,1 open drain)
VOEXP(H)
VOEXP(L)
High level input current
IIH
Low level input current
IIL
Reset pin high level input current IIH(RST)
Reset pin low level input current IIL(RST)
4th byte
Pull up (VDD)
IOEXP = 100 µA
VIN = VDD
VIN = 0
VRST = VDD
VRST = 0
0.9 × VDD
0.3
0.9 × VDD
1.0
1.0
V
0.1 × VDD V
0.1 × VDD
1.0
1.0
V
V
µA
µA
µA
µA
H bridge ON resistance
Chopping frequencyNote 1
RON IM = 100 mA, upper + lower
fOSC
6.0
Refer to table 1 (TYP.)
kHz
Internal reference voltage
VD delay timeNote 2
VREF
tVD
225 250 275 mV
250 ns
Sin wave peak output current
(reference value)Note 3
FIL pin voltageNote 4
FIL pin step voltageNote 4
H bridge turn on timeNote 5
H bridge turn off timeNote 5
IM
VEVR
VEVRSTEP
tONH
tOFFH
L = 15 mH/R = 70 ( 1 kHz)
RS = 6.8 , fOSC = 72.58 kHz
EVR = 220 mV (11100)
EVR = 200 mV (11010)
VREF = 250 mV external input
Minimum step
IM = 100 mA
53 mA
370 400 430 mV
20 mV
2.0 µs
2.0 µs
Notes 1. When data are less than 7 (000111), PWM chopping doesn’t do it, and output pulse doesn’t occur.
When data are beyong 49, PWM chopping frequency becomes a 225 kHz fixation.
2. By OSCIN and VD sync circuit
3. FB pin is monitored.
4. FIL pin is monitored. A voltage about twice that of the EVR value is output to the FIL pin.
5. 10% to 90% of the pulse peak value without filter capacitor (CFIL)
Data Sheet S14188EJ1V0DS00
3


3Pages


UPD16879 電子部品, 半導体
PIN CONFIGURATION
1 LGND
2 COSC
3 FILA
4 FILB
5 FILC
6 FILD
7 VREF
8 VDD
9 VM3
10 D2
11 FBD
12 D1
13 VM4
14 C2
15 FBC
16 C1
17 EXP0
18 EXP1
19 VREFsel
RESET
OSCOUT
OSCIN
SCLK
SDATA
LATCH
VD
VD
B2
FBB
B1
VM2
A2
FBA
A1
VM1
EXTβ
EXTα
PGND
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
µPD16879
6 Data Sheet S14188EJ1V0DS00

6 Page



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Link :


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