|
|
PDF UPD16857 Data sheet ( Hoja de datos )
| Número de pieza | UPD16857 | |
| Descripción | MONOLITHIC 6 channel H-BRIDGE DRIVER | |
| Fabricantes | NEC | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de UPD16857 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16857
MONOLITHIC 6 channel H-BRIDGE DRIVER
DESCRIPTION
µPD16857 is monolithic 6 channel H-bridge driver employing power MOS FETs in the output stages. The MOS
FETs in the output stage lower the saturation voltage and power consumption as compared with conventional drivers
using bipolar transistors.
In addition, a low-voltage malfunction prevention circuit is also provided that prevents the IC from malfunctioning
when the supply voltage drops. A 30-pin plastic shrink SOP package is adopted to help create compact and slim
application sets.
In the output stage H bridge circuits, two low-ON resistance H-bridge circuits for driving actuators, and another
three channels for driving sled motors and tilt control, and another channel for driving loading motor are provided,
making the product ideal for applications in DVD-ROM/DVD-RAM.
FEATURES
• Six H-bridge outputs employing power MOS FETs.
• High speed PWM drive corresponding: Operating input frequency 120 kHz (MAX.)
• Low voltage malfunction prevention circuit: Operating control block voltage under 2.5 V (TYP.)
• Loading into 38-pin shrink SOP (300 mil).
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)
Parameter
Control block supply voltage
Output block supply voltage
Input voltage
Output current
Power consumptionNote
Peak junction temperature
Storage temperature range
Symbol
Condition
VDD
VM
VIN
ID(pulse) PW ≤ 5 ms, Duty ≤ 20 %
PT
TCH(MAX)
Tstg
Rating
–0.5 to +6.0
–0.5 to +13.5
–0.5 to VDD+0.5
±1.0
1.0
150
–55 to +150
Note When mounted on a glass epoxy board (10 cm × 10 cm × 1 mm, 15 % copper foil)
Unit
V
V
V
A/ch
W
°C
°C
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. S13908EJ1V0DS00 (1st edition)
Date Published July 1999 N CP(K)
Printed in Japan
©
1999
1 page  
BLOCK DIAGRAM
IN1B
3
IN1A
2
VDD
1
µPD16857
IN3B
38
IN3A
37
IN4B
36
IN2A
4
5 IN2B
6 1A
7 GND
8 1B
9 VM
10 2A
11 GND
12 2B
13 VM
14 5A
15 GND
6A
ch2
Control
ch1 LVP ch3
Control
Control
ch4
Control
level
shift
level
shift
level
shift
level
shift
H
Bridge
(ch1)
Pre- Pre-
driver driver
Pre- Pre-
driver driver
H
Bridge
(ch3)
H
Bridge
(ch2)
Pre- Pre-
driver driver
Pre- Pre-
driver driver
H
Bridge
(ch4)
H Bridge (ch5)
Pre- Pre-
driver driver
H Bridge (ch5)
H Bridge (ch6)
Pre- Pre-
driver driver
H Bridge (ch6)
IN4A
35
VM 34
3B 33
GND 32
3A 31
VM 30
4B 29
GND 28
4A 27
VM 26
5B 25
GND 24
6B
16
ch5 level
level
ch6
Control
shift
shift Control
17
VMLD
18
IN5A
19
IN5B
SEL
20
SEL
21
IN6A
22
IN6B
Remark Plural terminal (VM, VMLD, GND) is not only 1 terminal and connect all terminals.
23
Data Sheet S13908EJ1V0DS00
5
5 Page 
µPD16857
The switching characteristics shown on the preceding pages are specified as follow (“output at one side” means
output B for H-bridge output A, or output A for output B).
[Rise time]
Rise time when the output at one side is fixed to the low level (specified on current ON).
[Fall time]
Fall time when the output at one side is fixed to the high level (specified on current ON).
[Rising delay time]
Rising delay time when the output at one side is fixed to the low level (specified on current ON).
[Falling delay time]
Falling delay time when the output at one side is fixed to the high level (specified on current ON).
[Change in rising delay time]
Change (difference) in the rising delay time between when the output at one side is fixed to the low level and when
the output at the other side is fixed to the high level.
[Change in falling delay time]
Change (difference) in the falling delay time between when the output at one side is fixed to the low level and when
the output at the other side is fixed to the high level.
[Rising delay time differential]
Difference in rising delay time between output A and output B.
[Falling delay time differential]
Difference in falling delay time between output A and output B.
Caution Because this LSI switches a high current at high speeds, surge may occur due to the VM and GND
wiring and inductance and degrade the performance of the LSI.
On the PWB, keep the pattern width of the VM and GND lines as wide and short as possible, and
insert the bypass capacitors between VM and GND at location as close to the LSI as possible.
Connect a low inductance magnetic capacitor (4700 pF or more) and an electrolytic capacitor of
10 µF or so, depending on the load current, in parallel.
Data Sheet S13908EJ1V0DS00
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet UPD16857.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| UPD16855A | DUAL HIGH-SIDE SWITCH FOR USB APPLICATION | NEC |
| UPD16855AG | DUAL HIGH-SIDE SWITCH FOR USB APPLICATION | NEC |
| UPD16855BC | DUAL HIGH-SIDE SWITCH FOR USB APPLICATION | NEC |
| UPD16855BG | DUAL HIGH-SIDE SWITCH FOR USB APPLICATION | NEC |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |