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UPD16835 の電気的特性と機能

UPD16835のメーカーはNECです、この部品の機能は「MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD16835
部品説明 MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT
メーカ NEC
ロゴ NEC ロゴ 




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UPD16835 Datasheet, UPD16835 PDF,ピン配置, 機能
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16835
MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT
The µPD16835 is a monolithic quad H bridge driver IC that employs a CMOS control circuit and a MOS FET output
circuit. Because it uses MOS FETs in its output stage, this driver IC consumes less power than conventional driver
ICs that use bipolar transistors.
Because the µPD16835 controls a motor by inputting serial data, its package has been shrunk and the number
of pins reduced. As a result, the performance of the application set can be improved and the size of the set has been
reduced.
This IC employs a current-controlled 64-step micro step driving method that drives stepper motor with low vibration.
The µPD16835 is housed in a 38-pin shrink SOP to contribute to the miniaturization of the application set.
This IC can simultaneously drive two stepper motors and is ideal for the mechanisms of camcorders.
FEATURES
• Four H bridge circuits employing power MOS FETs
• Current-controlled 64-step micro step driving
• Motor control by serial data (8 bytes × 8 bits) (original oscillation: 4-MHz input)
Data is input with the LSB first.
EVR reference setting voltage: 100 to 250 mV (@VREF = 250 mV) ... 4-bit data input (10-mV step)
Chopping frequency: 32 to 124 kHz ... 5-bit data input (4-kHz step)
Original oscillation division or internal oscillation selectable
Number of pulses in 1 VD: 0 to 252 pulses ... 6 bits + 2-bit data input (4 pulses/step)
Step cycle: 0.25 to 8,191.75 µs ... 15-bit data input (0.25-µs step)
• 3-V power supply. Minimum operating voltage: 2.7 V (MIN.)
• Low current consumption IDD: 3 mA (MAX.), IDD (reset): 100 µA (MAX.), IMO: 1 µA (MAX.)
• 38-pin shrink SOP (300 mil)
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Parameter
Symbol
Condition
Rating
Supply voltage
VDD
-0.5 to +6.0
VM -0.5 to +11.2
Input voltage
VIN
-0.5 to VDD + 0.5
Reference voltage
VREF
500
H bridge drive currentNote 1
IM (DC)
DC
±150
Instantaneous H bridge drive currentNote 1 IM (pulse)
PW 10 ms, Duty 5%
±300
Power consumptionNote 2
PT
1.0
Peak junction temperature
TCH (MAX)
150
Storage temperature
Tstg
-55 to +150
Notes 1. Permissible current per phase with the IC mounted on a PCB.
2. When the IC is mounted on a glass epoxy PCB (10 cm × 10 cm × 1 mm).
The information in this document is subject to change without notice.
Document No. G11594EJ1V0DS00 (1st edition)
Date Published August 1998 J CP(K)
Printed in Japan
Unit
V
V
V
mV
mA/phase
mA/phase
W
°C
°C
© 1998

1 Page





UPD16835 pdf, ピン配列
µPD16835
ELECTRICAL CHARACTERISTICS
DC Characteristics (Unless otherwise specified, VDD = 3.3 V, VM = 6.0 V, VREF = 250 mV, TA = 25°C, fCLK = 4 MHz,
COSC = 33 pF, CFIL = 1,000 pF, EVR = 100 mV (0000))
Parameter
Symbol
Off VM pin current
IMO (RESET)
VDD pin current
IDD
VDD pin current
IDD (RESET)
High-level input voltage
VIH
Low-level input voltage
VIL
Input hysteresis voltage
VH
Monitor output voltage 1
(EXTOUT α, β)
VOMα (H), VOMβ (H)
VOMα (L), VOMβ (L)
Monitor output voltage 2
(EXP 0 to 4: open drain)
VOEXP (H)
VOEXP (L)
High-level input current
IIH
Low-level input current
IIL
Reset pin high-level input current IIH (RST)
Reset pin low-level input current IIL (RST)
Input pull-down resistor
RIND
H bridge ON resistanceNote 1
Chopping frequency
(internal oscillation: COSC = 100 pF)
Step frequency
VD delayNote 2
Sine wave peak output
currentNote 3
RON
fOSC (1)
fOSC (2)
fSTEP
tVD
IM
FIL pin voltageNote 4
FIL pin step voltageNote 4
VEVR
VEVRSTEP
Condition
MIN.
No load, reset period
Output open
Reset period
LATCH, SCLK,
SDATA, VD, RESET,
OSCIN
0.7*VDD
5th byte
0.9*VDD
5th byte
Pull up (VDD)
IOEXP = 100 µA
VIN = VDD
VIN = 0
-1.0
VRST = VDD
VRST = 0
-1.0
LATCH, SCLK,
SDATA, VD
50
IM = 100 mA
DATA: 00000 (4th byte)
DATA: 11111 (4th byte) 100
Minimum step
L = 25 mH/R = 100 (1 kHz)
EVR = 200 mV (1010)
RS = 6.8 , fOSC = 64 kHz
EVR = 200 mV (1010)
Minimum step
370
TYP.
300
3.5
0
124
4
52
400
20
MAX.
1.0
3.0
100
0.3*VDD
0.1*VDD
VDD
0.1*VDD
0.06
1.0
200
5.0
150
250
430
Unit
µA
mA
µA
V
V
mV
V
V
V
V
mA
µA
µA
µA
k
kHz
kHz
ns
mA
mV
mV
AC Characteristics (Unless otherwise specified, VDD = 3.3 V, VM = 6.0 V, TA = 25°C, fCLK = 4 MHz)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
H bridge output circuit turn on time tONH
H bridge output circuit turn off time tOFFH
IM = 100 mANote 5
IM = 100 mANote 5
1.0 2.0
1.0 2.0
Notes 1. Total of ON resistance at top and bottom of output H bridge
2. By OSCIN and VD sync circuit
3. FB pin is monitored.
4. FIL pin is monitored. A voltage about twice that of the EVR value is output to the FIL pin.
5. 10% to 90% of the pulse peak value without filter capacitor (CFIL)
Unit
µs
µs
3


3Pages


UPD16835 電子部品, 半導体
µPD16835
I/O PIN EQUIVALENT CIRCUIT
Pin name
Equivalent circuit
VDD
Pin name
VDD
LATCH
SDATA
SCLK
Pad
Pull-down
resistor (125 )
OSCIN
RESET
Pad
Equivalent circuit
VDD
VDD
OSCOUT
EXTα
EXTβ
Pad
VDD
EXP0
EXP1
EXP2
EXP3
Pad
VDD
VREF
Pad
A1, A2
B1, B2
C1, C2
D1, D2
6
FILA
FILB
FILC
FILD
Pad
VDD
Buffer
VM
Parasitic diodes
Pad
FB

6 Page



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