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PDF UPD16682 Data sheet ( Hoja de datos )

Número de pieza UPD16682
Descripción 1/65 DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM
Fabricantes NEC 
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No Preview Available ! UPD16682 Hoja de datos, Descripción, Manual

DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD16682
1/65 DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM
DESCRIPTION
The µ PD16682 is a LCD controller/driver that includes enough RAM capacity to drive full-dot LCD. Each chip can
drive a full-dot LCD consisting of up to 132 x 65 dots.
This chip is suitable for cellular phones, Japanese or Chinese-language pagers, and other devices that display
Japanese or Chinese characters using either 16 x 16 or 12 x 12 dots per character.
FEATURES
LCD controller/driver with on-chip display RAM
Able to operate using +3-V single power supply
On-chip booster circuit: switchable between 3x and 4x modes
RAM for dot displays: 132 x 65 bits
Outputs : 132 segments, 65 commons
Serial or 8-bit parallel data inputs (switchable between 80 series and 68 series MPUs)
On-chip divider resistor
Selectable bias settings (can be set as 1/9 bias or 1/7 bias)
On-chip oscillation circuit
ORDERING INFORMATION
Part number
µ PD16682W-xxxNote
µ PD16682P-xxxNote
µ PD16682N-xxxNote-051
Package
Wafer
Chip
Standard TCP (output OLB: 0.15-mm pitch), for evaluation
Note The following four temperature gradients can be selected.
-001: –0.05 % / °C
-002: –0.1 % / °C
-003: –0.15 % / °C
-004: 0 % / °C
Remark Purchasing the above chip/wafer entails exchange of documents such as a separate memorandum or
product quality, so please contact one of our sales representative.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S13368EJ3V0DS00(3rd edition)
Date Published March 2000 NS CP(K)
Printed in Japan
The mark shows major revised points.
©
1998

1 page




UPD16682 pdf
µ PD16682
Pad
No.
Pad Name
117 COM1
118 COM0
119 COMS
120 DUMMY4
121 DUMMY5
122 SEG0
123 SEG1
124 SEG2
125 SEG3
126 SEG4
127 SEG5
128 SEG6
129 SEG7
130 SEG8
131 SEG9
132 SEG10
133 SEG11
134 SEG12
135 SEG13
136 SEG14
137 SEG15
138 SEG16
139 SEG17
140 SEG18
141 SEG19
142 SEG20
143 SEG21
144 SEG22
145 SEG23
146 SEG24
147 SEG25
148 SEG26
149 SEG27
150 SEG28
151 SEG29
152 SEG30
153 SEG31
154 SEG32
155 SEG33
156 SEG34
157 SEG35
158 SEG36
159 SEG37
160 SEG38
161 SEG39
162 SEG40
163 SEG41
164 SEG42
165 SEG43
166 SEG44
167 SEG45
168 SEG46
169 SEG47
170 SEG48
171 SEG49
172 SEG50
173 SEG51
174 SEG52
X [µ m]
4788
4788
4788
4788
4023
3930
3870
3810
3750
3690
3630
3570
3510
3450
3390
3330
3270
3210
3150
3090
3030
2970
2910
2850
2790
2730
2670
2610
2550
2490
2430
2370
2310
2250
2190
2130
2070
2010
1950
1890
1830
1770
1710
1650
1590
1530
1470
1410
1350
1290
1230
1170
1110
1050
990
930
870
810
Table 21. Pad Layout (2/3)
Y [µ m]
860
920
980
1073
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
Pad
Type
A
A
A
C
C
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Pad
No.
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
Pad Name
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
SEG101
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
X [µ m]
750
690
630
570
510
450
390
330
270
210
150
90
30
–30
–90
–150
–210
–270
–330
–390
–450
–510
–570
–630
–690
–750
–810
–870
–930
–990
–1050
–1110
–1170
–1230
–1290
–1350
–1410
–1470
–1530
–1590
–1650
–1710
–1770
–1830
–1890
–1950
–2010
–2070
–2130
–2190
–2250
–2310
–2370
–2430
–2490
–2550
–2610
–2670
Y [µ m]
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
1198
Pad
Type
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Data Sheet S13368EJ3V0DS00
5

5 Page





UPD16682 arduino
µ PD16682
4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS
The input/output circuit type of each pin and recommended connection of unused pins are shown in the following
table.
Pin Name
I/O
Recommended Connection of Unused Pins
Notes
P,/S
/CS1
CS2
/RD(E)
/WR (R,/W)
C86
D0 to D5
D6 (SCL)
D7 (SI)
A0
TESTOUT
/RES
CLS
Input
Input
Input
Input
Input
Input
Input/Output
Input/Output
Input/Output
Input
Output
Input
Input
Mode setting pin
Connect to VSS
Connect to VDD
Connect to VDD (80 series interface),
connect to VDD or VSS (serial interface)
Connect to VDD or VSS (serial interface)
Mode setting pin
Leave open (when using serial interface)
Data/command setting pin
Leave open
Connect to VDD
Mode setting pin
1
1
4
2
1
FR
FRS
/DOF
Input/Output
Output
Input/Output
Leave open (when using master mode, M,/S = H)
Leave open
Leave open (when using master mode, M,/S = H)
M,/S
CL
HPM
IRS
TEST1
Input
Input/Output
Input
Input
Input
Mode setting pin
Display clock
Mode setting pin
Mode setting pin
Leave open
1
3
1
1
4
TEST2
TEST3
TEST4
Input
Input
Output
Leave open
Leave open
Leave open
4
4
TEST5
Output
Leave open
Notes 1. Connect to VDD or VSS according to the selected mode.
2. Input microcontroller output from VDD or VSS according to the selected register.
3. This pin is an output when M,/S = H and CLS = H but should otherwise be used to input the display clock.
4. These pins are pulled down to VSS in the IC.
Data Sheet S13368EJ3V0DS00
11

11 Page







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