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UPD16663 の電気的特性と機能

UPD16663のメーカーはNECです、この部品の機能は「240-OUTPUT LCD COLUMN SEGMENT DRIVER WITH BUILT-IN RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD16663
部品説明 240-OUTPUT LCD COLUMN SEGMENT DRIVER WITH BUILT-IN RAM
メーカ NEC
ロゴ NEC ロゴ 




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UPD16663 Datasheet, UPD16663 PDF,ピン配置, 機能
DATA SHEET
MOS INTEGRATED CIRCUITS
µPD16663
240-OUTPUT LCD COLUMN (SEGMENT) DRIVER WITH BUILT-IN RAM
DESCRIPTION
The µPD16663 is a column (segment) driver device with built-in RAM. It is capable of driving a full-dot LCD.
There are 240 outputs that, with the 240 × 160 × 4-bit built-in display RAM, enable a 16-gray scale display. The
sixteen gray scales can be selected arbitrarily from a 49-stage palette. When combined with the µPD16667, this
device can drive displays of 240 × 160 to 480 × 320 dots.
FEATURES
• Built-in display RAM: 240 × 160 × 4 bits
• Logic voltage: 3.0 to 3.6 V
• Duty cycle: 1/160
• Number of outputs: 240
• Gray scales: 16 (selectable from a palette of 49)
• Memory management: Packed pixel
• Compatible with 8-bit/16-bit data buses
ORDERING INFORMATION
Part number
Package
µPD16663N-×××
TCP (TAB)
5
µPD16663N-051
2-side standard TCP
Remark The TCP's external shape is customized. To order the required shape, please contact
an NEC salesperson.
Document No.
Date Published
Printed in Japan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
S13392EJ1V0DS00 (1st edition)
December 1999 NS CP(K)
The mark 5 shows major revised points.
©
1998, 1999

1 Page





UPD16663 pdf, ピン配列
µPD16663
1. PIN FUNCTIONS
Classification
CPU Interface
3.3 V
Control signals
3.3 V
5.0 V
LCD drive
Power supply
Pin nameNote
D0 to D15
A0 to A16
/CS
/OE
/WE
/UBE
RDY
PL0
PL1
DIR
MS
BMODE
/REFRH
TEST
/RESET
/DOFF
OSC1
OSC2
STB
/FRM
PULSE
L1
L2
/DOUT
Y1 to Y240
GND
VCC1
VCC2
V0
V1
V2
I/O Function
I/O Data bus : 16 bits
I Address bus : 17 bits
I Chip select
I Read signal
I Write signal
I Upper byte enable
O Ready signal issued to CPU ("H" sets ready status)
I Specifies the LSI placement position (No. 0 to 3)
I Specifies the LSI placement position (No. 0 to 3)
I Specifies the direction of the LCD panel placement
I Selects between master/slave ("H" sets master mode)
I Selects the data bus bit ("H" sets 8 bits, "L" sets 16 bits)
I/O Self-diagnostics reset pin (Wired-OR connection)
I Test pin ("H" sets test mode, pull-down resistor is built-in)
I Reset signal
I Display OFF input signal
- For external resistor for oscillator
- For external resistor for oscillator
I/O Column driving signal (MS pin "H" sets output, MS pin "L" sets input)
I/O Frame signal (MS pin "H" sets output, MS pin "L" sets input)
I/O 25-gray-scale pulse modulation clock
I/O Row driver driving level select signal (line 1)
I/O Row driver driving level select signal (line 2)
O Display OFF output signal
O LCD drive output
- Ground (× 2 for 5 V, × 3 for 3.3 V)
- 5-V power supply
- 3.3-V power supply
- LCD drive analog power supply
- LCD drive analog power supply
- LCD drive analog power supply
Note
3.3-V pins : D0 to D15, A0 to A16, /CS, /OE, /WE, /UBE, RDY, BMODE, PL0, PL1, DIR, OSC1, OSC2, /RESET,
/DOFF, TEST, MS
5-V pins :STB, /FRM, L1, L2, /DOUT, PULSE
Remark N.C. = Non-connection
Data Sheet S13392EJ1V0DS00
3


3Pages


UPD16663 電子部品, 半導体
µPD16663
3. DATA BUS
The byte data ordering on the data bus is little endian, which is the format commonly used in most NEC and
Intel products.
(1) 16-bit data bus (BMODE = L)
Byte access
Address increases
as shown
D0 to D7
00000H
00002H
00004H
:
:
D8 to D15
00001H
00003H
00005H
:
:
Word access
Address increases
as shown
D0 to D7
00000H
00002H
00004H
:
:
D8 to D15
In the same way as access from the system can be performed in word (16-bit) and byte (8-bit) units, valid data
is indicated by D0 to D7 and/or D8 to D15, by means of the /UBE signal (higher byte enable) and A0.
/CS
H
L
L
L
L
/OE
×
L
H
H
×
/WE
×
H
L
H
×
/UBE
×
L
L
H
L
L
H
×
H
A0
×
L
H
L
L
H
L
×
H
MODE
Not Selected
Read
Write
Output Disable
I/O
D0 to D7
D8 to D15
Hi-z Hi-z
Dout
Dout
Hi-z Dout
Dout
Hi-z
Din Din
× Din
Din ×
Hi-z Hi-z
Hi-z Hi-z
Remark ×= Don't Care, Hi-z= High impedance
6 Data Sheet S13392EJ1V0DS00

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
UPD16661A

160-OUTPUT LCD COLUMN SEGMENT DRIVER WITH RAM

NEC
NEC
UPD16661AN

160-OUTPUT LCD COLUMN SEGMENT DRIVER WITH RAM

NEC
NEC
UPD16661AN-051

160-OUTPUT LCD COLUMN SEGMENT DRIVER WITH RAM

NEC
NEC
UPD16662

240 OUTPUT LCD COLUMN SEGMENT DRIVER WITH BUILT-IN RAM

NEC
NEC


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