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PDF UPD16654N Data sheet ( Hoja de datos )
| Número de pieza | UPD16654N | |
| Descripción | 150/154 OUTPUT TFT-LCD GATE DRIVE | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16654
150/154 OUTPUT TFT-LCD GATE DRIVE
The µPD16654 is a TFT-LCD gate driver. Because this gate driver has a level shift circuit for logic input, it can
output a high gate scanning voltage in response to a CMOS-level input.
Moreover, it can also drive both the XGA/SXGA panel (154 outputs) and SVGA panel (150 outputs) by changing
the number of outputs over between 150 and 154.
FEATURES
• High breakdown voltage output (ON/OFF range: VDD2-VEE2 = 40 V MAX.)
• 3.3 V CMOS level input
• Number of output select function (150/154 outputs)
ORDERING INFORMATION
Part Number
µPD16654N-×××
Package
TCP (TAB package)
The TCP’s external shape is customized. To order your TCP’s external shape, please contact an NEC salesperson.
Document No. S11647EJ1V0DS00 (1st edition)
Date Published May 1998 N CP(K)
Printed in Japan
© 1998
1 page  
µPD16654
Caution 2. Inserting bypass capacitor
Because the internal logic operates at a high voltage (VDD2-VEE1), insert a bypass capacitor of
about 0.1 µF between the respective power pins as shown below to secure the noise margin
of VIH and VIL.
VDD2
VCC
VSS
VEE2
0.1 µF
0.1 µF
0.1 µF
0.1 µF
VEE1
Do not input a switching signal to the Osel pin that selects the number of outputs. Connect this pin to VCC or VSS (VEE1).
5
5 Page 
7. SWITCHING CHARACTERISTICS WAVEFORM (R/L = H)
1/fmax.
PWCLK(H)
PWCLK(L)
CLK
50%
50%
50%
tSETUP
tHOLD
50%
STVL1/2
(STVR1/2)
STVR1/2
(STVL1/2)
tPLH1
50%
50%
tPHL1
50%
50%
tPLH2
tTLH
90%
tPHL2
tTHL
90%
On
OEn
On
10%
PWOE
10%
50%
50%
VEE1
tPLH3
tPHL3
VEE2
90%
10%
VEE1
µPD16654
VCC
VSS
VCC
VSS
VCC
VSS
VDD2
VEE2
VCC
VSS
VDD2
VEE2
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet UPD16654N.PDF ] | |
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