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PDF UPD16633B Data sheet ( Hoja de datos )
| Número de pieza | UPD16633B | |
| Descripción | 312 OUTPUT TFT-LCD SORCE DRIVER COMPATIBLE WITH 64 GRAY SCALES | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16633B
312 OUTPUT TFT-LCD SORCE DRIVER
(COMPATIBLE WITH 64 GRAY SCALES)
The µPD16633B is a source driver for TFT-LCDs capable of dealing with displays with 64 gray scales. Data input
is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000
colors by output of 64 values γ-corrected by an internal D/A converter and 5-by-2 external power modules. Because
the output dynamic range is as large as 9.8 VP-P, level inversion operation of the LCD’s common electrode is
rendered unnecessary. Also, to be able to deal with dot-line inversion when mounted on a single side, this source
driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively
output gray scale voltages of differing polarity. Assuring a maximum clock frequency of 45 MHz when driving at 3.0
V, this driver is applicable to XGA-standard TFT-LCD panels.
FEATURES
• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter
• Output dynamic range 9.8 VP-P min. (@VDD2 = 10.0 V)
• CMOS level input
• Input of 6 bits (gradation data) by 6 dots
• High-speed data transfer: fmax. = 45 MHz (internal data transfer speed when operating at 3.0 V)
• 312 outputs
• Apply for only dot inversion
• Display data inversion function (POL2 terminal.)
• Single bank arrangement is possible (loaded with slim TCP)
ORDERING INFORMATION
Part Number
µPD16633BN-×××
Package
TCP (TAB package)
The TCP’s external shape is customized. To order your TCP’s external shape, please contact a NEC salesperson.
Document No. S13214EJ2V0DS00 (2nd edition)
Date Published July 1998 N CP(K)
Printed in Japan
© 1998
1 page  
µPD16633B
Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order. Reverse
this sequence to shut down. (Simultaneous power application to VDD2 and V0 to V9 is
possible.)
2. To stabilize the supply voltage, please be sure to insert a 0.47 µF bypass capacitor between
VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion of
a bypass capacitor of about 0.01 µF is also advised between the γ -corrected power supply
terminals (V0, V1, V2, ···, V9) and VSS2.
5
5 Page 
µPD16633B
8. CAUTIONS ABOUT FRAME INVERSION
In the case of dot inversion, n frame last line and (n+1) frame first line is the same polarity.
When write the same polarity twice, there are two cases as follows.
(1) last line output in n frame > first line output in (n+1) frame → Possible to write
(2) last line output in n frame < first line output in (n+1) frame → Not possible to write
µPD16633B has charge buffer and discharge buffer, so need to inversion polarity and write in the case of both
ways.
Vertical intervals
STB n frame last line
(n+1) frame
first line
(n+1) frame
second line
POL Discharge buffer
Charge buffer
S2N
VCOM
Hi-z Hi-z Hi-z
STB
POL
S2N
n frame last line
Vertical intervals
(n+1) frame
first line
(n+1) frame
second line
VCOM
Hi-z Hi-z Hi-z Hi-z
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet UPD16633B.PDF ] | |
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