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UPD16602N の電気的特性と機能

UPD16602NのメーカーはNECです、この部品の機能は「312-OUTPUT TFT-LCD FULL COLOR DRIVER」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD16602N
部品説明 312-OUTPUT TFT-LCD FULL COLOR DRIVER
メーカ NEC
ロゴ NEC ロゴ 




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UPD16602N Datasheet, UPD16602N PDF,ピン配置, 機能
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16602
312-OUTPUT TFT-LCD FULL COLOR DRIVER
The µPD16602 is a TFT-LCD source driver with full color display capability. It is ideal for 1024 × 768 pixel (XGA) class
high definition displays. The internal circuit consists of 12 channels (4 × 3) of analog input pins, 12 channels of 16-bit shift
registers and 312 channels of sample & hold circuits (2 latch type).
Analog display signals are sampled in 12 channels simultaneously by the sample & hold circuits and they are output in
the next line. The output voltage of the sample & hold circuits is as great as 10.5 VP-P and maintains high accuracy with an
output deviation of ±20 mVMAX. Inputting analog display signals that been γ -processed in the previous stage signal
processing circuit allows realization of a high definition 256-gray-scale-equivalent full color display without requiring line
inversion.
FEATURES
• 4 × 3 (RGB)-channel analog input allows display signal input wiring to be reduced.
• High dynamic range (10.0 VP-PMIN. VDD2 = 11.0 V)
• High accuracy sample & hold circuits (output deviation; ±20 mVMAX., ±5.0 mVTYP.)
• High-speed sampling frequency (for both analog and digital; fmax. = 20 MHzMIN.)
• Low power control (reduction of output buffer bias current) function on chip
(operating power consumption; 82 mWTYP., VDD2 = 12.5 V)
• Bi-directional data store function on chip
• Corresponding to high-density mounting (slim TCP)
ORDERING INFORMATION
Part Number
µPD16602N- × × ×
TCP
Package
Document No. S10671EJ1V0DS00 (1st edition)
Date Published August 1998 N CP(K)
Printed in Japan
© 1998

1 Page





UPD16602N pdf, ピン配列
SAMPLE & HOLD + OUTPUT BUFFER CIRCUIT 2
DR0 to DR3
DG0 to DG3
DB0 to DB3
HS
12
Sample and hold
+ Output buffer circuit
S1
S3
S5
PL/NL
S/D
PL/NL
S311
Sample and hold
+ Output buffer circuit
PL/NL
S2
S4
S6
S312
µPD16602
3


3Pages


UPD16602N 電子部品, 半導体
µPD16602
4. NOTES ON USE
(1) In order to prevent latch up breakdown, power should be applied in the order of:
VDD1 logic input VDD2(D), (A) VBIAS1,2, VCOM analog display signal input, and turned off in the reverse
order.
This order should also be observed in transition periods.
(2) VSS1, VSS2(D), VSS2(A) and VSS2(C) are connected in the diffusion layer, but also be sure to connect them
externally.
Do not share the sample & hold ground VSS2(C) with other ground wiring on the mount board, but connect it to
the edge to the signal board. There is a possibility of high-voltage or logic type noise being superimposed
onto the sample & hold circuit, damaging the analog characteristics (output deviation, etc.).
(3) Likewise, to prevent the sample & hold characteristics from deteriorating, insert a bypass capacitor of 0.1 µF
between VDD1 and VSS1, and approximately 0.1 µF between VDD2(D), (A) and VSS2(D), (A). An unstable power
supply may cause a driver through current, preventing the output range of the output buffer from being
sufficiently secured. Therefore, determine the capacitance of the bypass capacitor after a thorough
evaluation.
(4) When LPC = “H”, stable current supply of the output buffer may be shut off, which will impede normal
negative feedback, and when the LCD panel load is small, the output voltage may become abnormal.
Normal operation is assured with approximately 10 k+ 50 pF, but when the time constant is smaller than
this, please set LPC = “L”.
(5) Data input/output relationship
As shown below, irrespective of right shift and left shift.
Output
S1
S2
S3
S4
S5
S6
Data
DR0
DB0
DG0
DR1
DB1
DG1
S309
DG2
S310
DR3
S311
DB3
S312
DG3
(6) Bias control method
Externally applying a voltage to pins BIAS1 and BIAS2 can control the output buffer current consumption. In
this case, the analog characteristics (output deviation, driving capability, response speed, etc.) will not
change. Please refer to the configuration in the figure below for the actual circuit. Also refer to the same
configuration for the VCOM voltage input circuit. Current per driver IC is as follws.
VDD2
100 µAMIN.
(per IC)
VBIAS1, VBIAS2, VCOM
0.01 µF
6

6 Page



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共有リンク

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部品番号部品説明メーカ
UPD16602

312-OUTPUT TFT-LCD FULL COLOR DRIVER

NEC
NEC
UPD16602

312-OUTPUT TFT-LCD FULL COLOR DRIVER

NEC
NEC
UPD16602N

312-OUTPUT TFT-LCD FULL COLOR DRIVER

NEC
NEC


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