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UPD16434G-001-12 の電気的特性と機能

UPD16434G-001-12のメーカーはNECです、この部品の機能は「1/8/ 1/16 DUTY LCD CONTROLLER/DRIVER」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD16434G-001-12
部品説明 1/8/ 1/16 DUTY LCD CONTROLLER/DRIVER
メーカ NEC
ロゴ NEC ロゴ 




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UPD16434G-001-12 Datasheet, UPD16434G-001-12 PDF,ピン配置, 機能
DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD16434
1/8, 1/16 DUTY LCD CONTROLLER/DRIVER
DESCRIPTION
µ PD16434 is LCD controller/driver containing the interfacing features for a dot-matrix mode 8-, 16-time division
LCD and a microprocessor. µ PD16434 contains a 5- by 7-dot matrix character generator corresponding to
ASCII/JIS. Therefore, user original patterns can be easily displayed.
FEATURES
DOT matrix LCD controller/driver
8- or 16-time division drive possible with a single chip
8-time-division : 400 (50 by 8) dots
16-time-division : 672 (42 by 16) dots
8- or 16-time division drive possible with no chip
8-time-division : n × 400 (50 by 8) dots
16-time-division : n × 800 (50 by 16) dots
Display data storage RAM : 20 × 50 × 8 bits
Programmer specified dot (graphic) display
Capable of alphanumeric and symbolic displays thorough built-in ROM (5 by 7 dots)
160 characters
Parallel data input/output (Switch able between 4 and 8 bits)
Cursor manipulation command
Upgraded version of µ PD7228, µ PD7228A, µ PD7229, µ PD7229A
ORDERING INFORMATION
Part Number
Package
µ PD16434G-xxx-12
80-PIN PLASTIC QFP (14 × 20)
µ PD16434G-001-12
80-PIN PLASTIC QFP (14 × 20), Standard ROM code
5
µ PD16434GF-xxx-3B9
80-PIN PLASTIC QFP (14 × 20)Note
5 µ PD16434GF-001-3B9 80-PIN PLASTIC QFP (14 × 20), Standard ROM code Note
Note This package is only available in European market.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S10299EJ4V0DS00 (4th edition)
Date Published April 2000 NS CP(K)
Printed in Japan
The mark 5 shows major revised points.
1994, 1999

1 Page





UPD16434G-001-12 pdf, ピン配列
R-S
R-NS
R0/R8 to R7/R15
8
ROW DRIVER
16
R8/C49 to R15/C42
8
ROW/COLUMN
DRIVER
16 8
C0 to C41
42
COLUMN DRIVER
16
42
C-S
C-NS
VDD
VLC1
VLC2
VLC3
VLC4
VLC5
VSS
SYNC
CLOCK
LCD
VOLTAGE
CONTROL
R-S
R-NS
C-S
C-NS
LCD TIMING
CONTROL
16
STOP
CLOCK
BUFFER
SYSTEM
CLOCK
CONTROL
50
DATA MEMORY
16 BANK 0
(50 x 8 BITS)
50
DATA MEMORY
BANK 1
(50 x 8 BITS)
8
COMMAND
DECODER
8
DATA
POINTER
CHARACTER
GENERATOR
(160 x 5 x 7 BITS)
7
88
8
SERIAL/PARALLEL INTERFACE


3Pages


UPD16434G-001-12 電子部品, 半導体
µ PD16434
1. PIN FUNCTIONS
1.1 D0 to D3 (Data Bus) … 3-state input/output
In the parallel interface mode, these pins serve as 4-bit parallel data input/output pins.
Data on the D0 to D3 lines is read at the /STB signal rising edge. The 4-bit data, read at the first rising edge of the
/STB, is loaded into the upper 4 bits of the serial/parallel register, and the data read at the second rising edge is loaded
into the lower 4 bits of the register.
The serial/parallel register contents are output to the D0 to D3 pins in synchronization with the /STB signal falling
edge. In the same manner as read operation, the upper 4 bits of the serial/parallel register are output in the first /STB
signal falling edge, and the lower 4bits are output in the second /STB falling edge.
In the serial interface mode, the D0 serves as the serial data input pin (SI), and the D3 pin serves as the serial
data output pin (SO).
The D1 pin serves as the parallel/serial interface mode selection pin (P, /S), and the D2 pin serves as the chip
address enable pin (CAE).
1.2 SI (Serial Data In) … Also serves as D0 input
This pin serves as the serial data input pin in the serial interface mode. Data on the SI line is loaded into the
serial/parallel register at the /SCK rising edge. The first data becomes the MSB. This is a Schmitt trigger input with
hysteresis, in order to prevent erroneous operation caused by noise.
1.3 SO (Serial Data Out) … Also serves as D3 output
This pin serves as the serial data output pin in the serial interface mode. The serial/parallel register contents are
output to the SO pin with the MSB first in synchronization with the /SCK pin falling edge.
1.4 P, /S (Parallel/Serial Select) … Also serves as D1 input
This pin is sampled at the RESET signal falling edge (when the reset is released). If this pin is high, the parallel
interface mode is set. If it is low, the serial interface mode is set. This is a Schmitt trigger input with hysteresis in
order to prevent erroneous operation caused by noise.
1.5 CAE (Chip Address Enable) … Also serves as D2 input
The CAE input has a meaning, if P, /S input is low (when the serial interface mode is specified) at the RESET
signal falling edge (when reset is released). If the CAE signal is high at this timing, the chip address function is enabled.
If the CAE signal is low, the chip address function is disabled. This is a Schmitt trigger input with
hysteresis in order to prevent erroneous operation caused by noise.
1.6 CA0, CA1 (Chip Address) … Input
This is the input pin used to allocate the inherent address to select each µ PD16434 chip, when interfacing with
the CPU in a multi-chip configuration. In the parallel interface mode, CA0 and CA1 inputs are compared with the
chip address information sent from the CPU, regardless of the CAE input. In the serial interface mode, these inputs are
compared with the chip address information sent from the CPU, when the chip address selection function is enabled by
the CAE input.
6 Data Sheet S10299EJ4V0DS00

6 Page



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部品番号部品説明メーカ
UPD16434G-001-12

1/8/ 1/16 DUTY LCD CONTROLLER/DRIVER

NEC
NEC


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