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PDF UPD16340 Data sheet ( Hoja de datos )
| Número de pieza | UPD16340 | |
| Descripción | 96-BIT AC-PDP DRIVER | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD16340
96-BIT AC-PDP DRIVER
DESCRIPTION
The µ PD16340 is a high withstand voltage CMOS driver designed for use with a flat display panel such as a PDP,
VFD, or EL panel. It consists of a 96-bit bi-directional shift register, 96-bit latch and high withstand voltage CMOS
driver. The logic block operates with a 5-V power supply interface (CMOS level input) so that it can be directly
connected to a gate array and microcontroller. The driver block provides a high withstand voltage output: 80 V, +50/–
75 mA MAX. The logic and driver blocks are made of CMOS circuits, consuming lower power.
FEATURES
• Circuit configuration switched by the IBS pin between three 32-bit bi-directional shift registers and six 16-bit
bidirectional shift registers.
• Data control with transfer clock (external) and latch
• High-speed data transfer (fMAX. = 40 MHz MIN. at data latch)
(fMAX. = 25 MHz MIN. at cascade connection)
• High withstand output voltage (80 V, +50/–75 mA MAX.)
• 5-V CMOS input interface
• High withstand voltage CMOS structure
• ORDERING INFORMATION
Part Number
µ PD16340
Package
Module
Caution Consult an NEC sales representative regarding the module. Since the module characteristics is
based on the module specifications, there may be differences between the contents written in this
document and real characteristics.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S13685EJ1V0DS00 (1st edition)
Date Published December 1999 NS CP (K)
Printed in Japan
The mark • shows major revised points.
©
1998,1999
1 page  
µ PD16340
TRUTH TABLE
Shift Register Block
Input
R,/L CLK
H↑
H H or L
L↑
L H or L
Output
A
Input
Output Note2
Output
B
Output Note1
Output
Input
Shift Register
Right shift operation performed
Hold
Left shift operation performed
Hold
Notes 1. On the rising edge of the clock, the data of S91-S93 (S85-S90) is shifted to S94-S96 (S91-S96), and is output
from B1-B3 (B1-B6) (The parenthesized pins are used in 6-bit input mode.).
2. On the rising edge of the clock, the data of S4-S6 (S7-S12) is shifted to S1-S3 (S1-S6), and is output from
A1-A3 (A1-A6) (The parenthesized pins are used in 6-bit input mode.).
Latch Block
/LE
↓
H or L
Output State of Latch Section (/Ln)
Latch Sn data
Hold latch (output) data
Driver Block
A (B)
/HBLK
/LBLK
HZ
x LH
x xL
x xx
L HH
H HH
Remark x : H or L, H : High level, L : Low level
L
L
H
L
L
Output State of Driver Block
All driver output : H
All driver output : L
All driver output : High Impedance
L
H
Data Sheet S13685EJ1V0DS00
5
5 Page 
µ PD16340
Timing Requirement (TA = –40 to +85 °C, VDD1 = 4.5 to 5.5 V, VSS1 = VSS2 = 0 V, tr = tf = 6.0 ns)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Clock Pulse Width
Latch Enable Pulse Width
Blank Pulse Width
HZ Pulse Width
/CLR Pulse Width
Data Setup Time
Data Hold Time
Latch Enable Time
• /CLR Timing
PWCLK(H)
PWCLK(L)
PW/LE(H)
PW/LE(L)
PW/BLK
PWHZ
PW/CLR
tSETUP
tHOLD
t/LE1
t/LE2
t/CLR
/HBLK, /LBLK
RL = 10 kΩ
12
12
200
3.3
12
4
6
12
12
6
Unit
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
Data Sheet S13685EJ1V0DS00
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet UPD16340.PDF ] | |
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