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UPC8105GR の電気的特性と機能

UPC8105GRのメーカーはNECです、この部品の機能は「UP-CONVERTER WITH AGC FUNCTION QUADRATURE MODULATOR IC FOR DIGITAL MOBILE COMMUNICATION SYSTEMS」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPC8105GR
部品説明 UP-CONVERTER WITH AGC FUNCTION QUADRATURE MODULATOR IC FOR DIGITAL MOBILE COMMUNICATION SYSTEMS
メーカ NEC
ロゴ NEC ロゴ 




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UPC8105GR Datasheet, UPC8105GR PDF,ピン配置, 機能
DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µPC8105GR
400 MHz QUADRATURE MODULATOR
FOR DIGITAL MOBILE COMMUNICATION
DESCRIPTION
The µPC8105GR is a sillicon monolithic integrated circuit designed as quadrature modulator for digital mobile
communication systems. This modulator housed in a 16 pin plastic SSOP that is easy to install and contributes to
miniaturizing the system.
The device has power save function and can operates 2.7 to 5.5 V supply voltage to realize low power
consumption.
FEATURES
Internal 90° phase shifter is accurate over an IF range from 100 MHz to 400 MHz.
Wide supply voltage range: VCC = 2.7 to 5.5 V.
Low operation current: ICC = 16 mA (typ.).
16 pin plastic SSOP suitable for high density surface mounting.
Low current in sleep mode
APPLICATION
IF modulator for Digital cellular phone (PDC, IS-54, GSM etc..)
IF modulator for Digital cordless phone (PHS, PCS etc..)
ORDERING INFORMATION
PART NUMBER
µPC8105GR-E1
PACKAGE
SUPPLYING FORM
16 pin plastic SSOP (225 mil) Carrier tape width 12 mm. Q’ty 2.5 kp/Reel
Pin 1 indicated pull-out direction of tape.
To order evaluation samples, please contact your local NEC sales office. (Part number for sample order:
µPC8105GR)
Caution electro-static sensitive device
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. P10807EJ3V0DS00 (3rd edition)
Date Published October 1999 N CP(K)
Printed in Japan
The mark shows major revised points.
©
1995, 1999

1 Page





UPC8105GR pdf, ピン配列
µPC8105GR
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage
Power Save Voltage
Power Dissipation
Operating Temperature
Storage Temperature
SYMBOL
VCC
VPS
PD
Top
Tstg
RATING
6.0
6.0
310
40 to +85
55 to +150
UNIT
V
V
mW
°C
°C
TEST CONDITIONS
TA = +25 °C
TA = +25 °C
TA = +85 °C*1
*1: Mounted on 50 × 50 × 1.6 mm double copper clad epoxy glass board
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Operating Temperature
Modulator Output Frequency
LO1 Input Frequency
I/Q Input Frequency
SYMBOL
VCC
TA
fMODout
fLO1in
fI/Qin
MIN.
2.7
40
100
DC
TYP.
3.0
+25
MAX.
5.5
+85
400
10
UNIT
V
°C
MHz
MHz
TEST CONDITIONS
PLOin = 10 dBm
PI/Qin = 600 mVp-p MAX (Single ended)
ELECTRICAL CHARACTERISTICS (TA = +25 °C, VCC = 3.0 V, Unless Otherwise Specified VPS 1.8 V)
PARAMETER
Circuit Current
Circuit Current at Power
Save Mode
Output Power
LO Carrier Leak
Image Rejection
(Side Band Leak)
SYMBOL
ICC
ICC(PS)
MIN.
10
TYP.
16
0.1
MAX.
21
5
UNIT
mA
µA
TEST CONDITIONS
No input signal
VPS 1.0 V
PMODout
LOL
ImR
21.0
16.5
40
40
12.0
30
30
dBm
dBc
dBc
I/Q DC = 1.5 V
PI/Qin = 500 mVp-p (Single ended)
Data Sheet P10807EJ3V0DS00
3


3Pages


UPC8105GR 電子部品, 半導体
µPC8105GR
PIN EXPLANATION
ASSIGN- SUPPLY PIN
PIN NO. MENT
VOL. (V) VOL.(V) FUNCTION AND APPLICATION
13 GND
14
0
Connect to the ground with
minimum inductance.
Track length should be kept as
short as possible.
15
Power
VP/S
Save
Power save control pin can be
controlled ON/SLEEP state with
bias as follows;
VP/S (v)
1.8 to 5.5
0 to 1.0
STATE
ON
SLEEP
16 VCC 2.7 to Supply voltage pin for modulator.
5.5 Internal regulator can be kept
stable condition of supply bias
against the variable temperature
or VCC.
EQUIPMENT CIRCUIT
15
EXPLANATION OF INTERNAL FUNCTION
BLOCK
90° PHASE
SHIFTER
FUNCTION/OPERATION
Input signal from LO is send to digital
circuit of T-type flip-flop through frequency
doubler. Output signal from T-type F/F is
changed to same frequency as LO input
and that have quadrature phase shift, 0°,
90°, 180°, 270°. These circuits have
function of self phase correction to make
correctly quadrature signals.
BLOCK DIAGRAM
from LOin
×2
÷2 F/F
BUFFER AMP.
Buffer amplifiers for each phase signals to
send to each mixers.
MIXER
ADDER
Each signals from buffer amp. are
quadrature modulated with two double-
balanced mixers.
High accurate phase and amplitude inputs
are realized to good performance for image
rejection.
Output signals from each mixers are added
with adder and send to final amplifier.
I
I
Q
Q
to MODout
6 Data Sheet P10807EJ3V0DS00

6 Page



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