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UPC4093G2 の電気的特性と機能

UPC4093G2のメーカーはNECです、この部品の機能は「J-FET INPUT LOW-OFFSET OPERATIONAL AMPLIFIER」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPC4093G2
部品説明 J-FET INPUT LOW-OFFSET OPERATIONAL AMPLIFIER
メーカ NEC
ロゴ NEC ロゴ 




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UPC4093G2 Datasheet, UPC4093G2 PDF,ピン配置, 機能
DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µPC4093
J-FET INPUT LOW-OFFSET OPERATIONAL AMPLIFIER
The µPC4093 operational amplifier is a high-speed version of the µPC4091. NEC's unique high-speed PNP
transistor (fT = 300 MHz) in the output stage realizes a high slew rate of 25 V/µs under voltage-follower conditions
without an oscillation problem. Zener-zap resistor trimming in the input stage produces excellent offset voltage and
temperature drift characteristics.
With AC performance characteristics that are two times better than conventional bi-FET operation amplifiers, the
µPC4093 is ideal for fast integrators, active filters, and other high-speed circuit applications.
FEATURES
• Stable operation with 220 pF capacitive load
• Low input offset voltage and offset voltage null
capability
±2.5 mV (MAX.)
±7 µV/°C (TYP.) temperature drift
• Very low input bias and offset currents
• Low noise : en = 19 nV/ Hz (TYP.)
• Output short circuit protection
• High input impedance ... J-FET Input Stage
• Internal frequency compensation
• High slew rate: 25 V/µs (TYP.)
ORDERING INFORMATION
Part Number
µPC4093C
µPC4093G2
EQUIVALENT CIRCUIT
(2)
II
Q1
Q2
IN
(3)
Q5
Q3 Q4
(1) (5)
OFFSET
NULL
TRIMMED
OFFSET
NULL
Package
8-pin plastic DIP (300 mil)
8-pin plastic SOP (225 mil)
Q6
Q7
C1
D1
V+
(7)
Q9
OUT
(6)
Q10
HIGH SPEED
PNP
Q8
(4)
V
PIN CONFIGURATION
(Top View)
µPC4093C, 4093G2
OFFSET
NULL
1
8 NC
II 2
7 V+
IN 3
+
6 OUT
V4
OFFSET
5 NULL
Remark NC : No Connection
The information in this document is subject to change without notice.
Document No. G13906EJ1V0DS00 (1st edition)
Date Published December 1998 N CP(K)
Printed in Japan
©
1998

1 Page





UPC4093G2 pdf, ピン配列
µPC4093
ELECTRICAL CHARACTERISTICS (TA = 25 °C, V± = ±15 V)
Parameter
Input Offset Voltage
Input Offset CurrentNote 7
Input Bias CurrentNote 7
Large Signal Voltage Gain
Supply Current
Common Mode Rejection Ratio
Supply Voltage Rejection Ratio
Output Voltage Swing
Common Model Input Voltage Range
Slew Rate
Unity Gain Frequency
Input Equivalent Noise Voltage Density
Input Offset Voltage
Average VIO Temperature Drift
Input Offset CurrentNote 7
Input Bias CurrentNote 7
Symbol
VIO
IIO
IB
AV
ICC
CMR
SVR
Vom
Conditions
RS 50
RL 2 k, VO = ±10 V
IO = 0 A
RL 10 k
RL 2 k
VICM
SR
funity
en
VIO
VIO/T
IIO
IB
AV = 1
RS = 100 , f = 1 kHz
RS 50 , TA = –20 to +70 °C
TA = –20 to +70 °C
TA = –20 to +70 °C
TA = –20 to +70 °C
MIN.
25000
70
70
±12
±10
±11
TYP.
±1
±25
50
200000
2.5
100
100
+14.0
–13.3
+13.5
–12.8
+14
–12
25
6
19
±7
MAX.
±2.5
±100
200
3.4
±5
±2
7
Unit
mV
pA
pA
mA
dB
dB
V
V
V
V/µs
MHz
nV/Hz
mV
µV/°C
nA
nA
Notes 7. Input bias currents flow into IC. Because each currents are gate leak current of P-channel J-FET on input
stage. And that are temperature sensitive. Short time measuring method is recommendable to maintain
the junction temperature close to the operating ambient temperature.
3


3Pages


UPC4093G2 電子部品, 半導体
PACKAGE DRAWINGS
8PIN PLASTIC DIP (300 mil)
8
5
µPC4093
14
A
IP
J
K
L
H
G
C
B
F
D NM
M
R
NOTES
1) Each lead centerline is located within 0.25 mm (0.01 inch) of
its true position (T.P.) at maximum material condition.
2) ltem "K" to center of leads when formed parallel.
ITEM MILLIMETERS INCHES
A 10.16 MAX. 0.400 MAX.
B
1.27 MAX.
0.050 MAX.
C 2.54 (T.P.) 0.100 (T.P.)
D
0.50±0.10
0.020
+0.004
–0.005
F 1.4 MIN.
0.055 MIN.
G 3.2±0.3
0.126±0.012
H
0.51 MIN.
0.020 MIN.
I
4.31 MAX.
0.170 MAX.
J
5.08 MAX.
0.200 MAX.
K 7.62 (T.P.) 0.300 (T.P.)
L 6.4
0.252
M
0.25+–00..0150
0.010
+0.004
–0.003
N 0.25
0.01
P 0.9 MIN.
0.035 MIN.
R 0~15°
0~15°
P8C-100-300B,C-1
6

6 Page



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部品番号部品説明メーカ
UPC4093G2

J-FET INPUT LOW-OFFSET OPERATIONAL AMPLIFIER

NEC
NEC


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