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PDF UPB1009K Data sheet ( Hoja de datos )
| Número de pieza | UPB1009K | |
| Descripción | NECs LOW POWER GPS RF RECEIVER BIPOLAR ANALOG + INTEGRATED CIRCUIT | |
| Fabricantes | NEC | |
| Logotipo |  |
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NEC’s LOW POWER
GPS RF RECEIVER
BIPOLAR ANALOG + INTEGRATED CIRCUIT
UPB1009K
DESCRIPTION
The µPB1009K is a silicon monolithic IC developed for GPS receivers. This IC integrates a full VCO, second IF
filter, 4-bit ADC, and digital control interface to reduce cost and mounting space. In addition, its power consumption
is low.
Moreover, use of a TCXO with frequency of 16.368 MHz/16.384 MHz, 14.4 MHz, 19.2 MHz, or 26 MHz switchable
with an on-chip divider is possible.
NEC’s stringent quality assurance and test procedures ensure the highest reliability and performance.
FEATURES
• Double conversion
• Multiple system clocks
• A/D converter
• High-density RF block
• Supply voltage
• Low current consumption
• High-density surface mountable
: fREFin = 16.368 MHz, f1stIFin = 61.380 MHz, f2ndIFin = 4.092 MHz
: fREFin = 14.4, 16.384, 19.2, 26 MHz, f1stIFin = 62.980 MHz, f2ndIFin = 2.556 MHz
: On-chip switchable frequency divider (1/N = 100, 3/256, 9/1024, 65/4096)
: On-chip 4-bit A/D converter
: On-chip VCO tank circuit and 2ndIF filter
: VCC = 2.7 to 3.3 V
: ICC = 26.0 mA TYP. @ VCC = 3.0 V, N = 100
: 44-pin plastic QFN
APPLICATIONS
• Consumer use GPS receiver of reference frequency 16.368 MHz, 2nd IF frequency 4.092 MHz
• Consumer use GPS receiver of reference frequency 14.4, 16.384, 19.2, 26 MHz, 2ndIF frequency 2.556 MHz
Caution Observe precautions when handling because these devices are sensitive to electrostatic discharge.
1 page  
UPB1009K
PIN EXPLANATION
Pin Pin Name
No.
1 PreAMPout
2 Rext
3 RegGND
42 PreAmpVCC
43 PreAmpGND
44 PreAmpin
Function and Application
Output pin of preamplifier.
Connect a resistor for the reference
constant-current power supply to this pin.
Ground this pin at 22 kΩ.
Ground pin for regulator.
Power supply voltage pin for preamplifier.
Connect a bypass capacitor to this pin to
reduce the high-frequency impedance.
Ground pin of preamplifier.
Input pin of preamplifier.
44
Internal Equivalent Circuit
1 42
2
4 1stMIXin
5 1stMIXGND
40 1stMIXVCC
41 1stIFout
1stMIX input pin.
Ground pin for first MIX.
Power supply voltage pin for RF mixer.
Connect a bypass capacitor to this pin to
reduce the high-frequency impedance.
Output pin of RF mixer. Insert an IFSAW
filter between this pin and pin 37. The
VCO oscillation signal can be monitored on
this pin.
40
4
5
43 3
Gibert
Cell
Bias
41
5
5 Page 
UPB1009K
POWER-DOWN CONTROL MODE
The µPB1009K consists of an RF block, an IF block, and a PLL block. By controlling reduction of power to each block (by
applying a voltage to the PD1 and PD2 pins), the following four modes can be used.
Mode
No.
1
2
3
4
Mode Name
Active mode
Calibration mode
Warm-up mode
Sleep mode
Test Conditions
PD1 PD2
LH
HH
HL
LL
RF Block
ON
OFF
OFF
OFF
IF Block
(IF + ADC)
ON
ON
OFF
OFF
PLL Block
ON
ON
ON
OFF
Caution To use only the active mode and sleep mode, fix PD1 to L and select the desired mode with PD2.
REFERENCE CLOCK CONTROL MODE
The divided frequency can be selected as follows so that it can be shared with the TCXO of each system.
TCXO Frequency
16.368 MHz (GPS)
16.384 MHz (GPS)
19.2 MHz (W-CDMA)
14.4 MHz (PDC)
26 MHz (GSM)
Test Conditions
PD1 PD2
LL
LH
HL
HH
1/N Phase Comparison Frequency
1/100
3/256
9/1024
65/4096
16.368 MHz
16.384 MHz
19.2 MHz
14.4 MHz
26 MHz
Caution When the reference clock frequency is 16.368 MHz, the 1stIF frequency and 2ndIF frequency are 61.38
MHz and 4.092 MHz, respectively. They are respectively 62.98 MHz and 2.556 MHz in all other cases.
11
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet UPB1009K.PDF ] | |
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