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UPB1007KのメーカーはETCです、この部品の機能は「PLL FREQUENCY SYNTHESIZER」です。 |
部品番号 | UPB1007K |
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部品説明 | PLL FREQUENCY SYNTHESIZER | ||
メーカ | ETC | ||
ロゴ | |||
このページの下部にプレビューとUPB1007Kダウンロード(pdfファイル)リンクがあります。 Total 8 pages
NEC's 3 V DUAL
DOWNCONVERTER AND UPB1007K
PLL FREQUENCY SYNTHESIZER
FEATURES
DESCRIPTION
• INTEGRATED RF BLOCK:
LNA, RF & IF Downconverter + PLL frequency
synthesizer
• STATE OF THE ART 25 GHz fT UHS0 BIPOLAR
PROCESS
• DOUBLE-CONVERSION: f1stIF = 61.380 MHz
f2ndIF = 4.092 MHz
• ADJUSTABLE GAIN: 20 dB range MIN
• FIXED DIVISION PRESCALER
• LOW POWER CONSUMPTION: 25 mA @ 3 V
NEC's UPB1007K is a Silicon RFIC designed for low cost GPS
receivers. The IC combines an LNA, followed by a double-
conversion RF/IF downconverter block and a PLL frequency
synthesizer on one chip. The device operates on a 3V supply
voltage and is housed in a small 36 pin QFN (Quad Flat No-
lead) package, resulting in low power consumption and re-
duced board space. The device is manufactured using the
state of the art UHS0 25 GHz fT silicon bipolar process.
NEC's stringent quality assurance and test procedures en-
sure the highest reliability and performance.
• SMALL 36 PIN QFN PACKAGE
Flat lead style for better performance
APPLICATIONS
• TAPE AND REEL PACKAGING AVAILABLE
• LOW POWER HANDHELD GPS RECEIVER
• IN-VEHICLE NAVIGATION SYSTEMS
• PC/PDA+GPS INTEGRATION
ELECTRICAL CHARACTERISTICS (TA = 25°C, VCC = 3.0 V, unless otherwise specified)
PART NUMBER
PACKAGE OUTLINE
UPB1007K
QFN-36
SYMBOLS
PARAMETERS AND CONDITIONS
UNITS
MIN
TYP
MAX
ICC Total Circuit Current, No Signals
mA
25 31
VCC Supply Voltage
V 2.7
3.0
3.3
LNA (fRFin = 1575.42 MHz, ZL = ZS = 50 Ω)
ZLNAin
RF Input Impedance of LNA
Ω 28 - j38
ZLNAop RF Output Impedance of LNA
Ω 85 - jx6
P1dBLNA 1 dB Compression, Input matched
dBm
-22
PGLNA Power Gain LNA, Input matched, PRFin = -60 dBm
dB
14
15
NFLNA Noise Figure of LNA, Input matched
dB
2.8
Mixer (fRFin = 1575.42 MHz, f1stLOin = 1636.80 MHz, PLO = -10 dBm, f1stIF = 61.38 MHz, ZL = ZS = 50 Ω)
ZMIXin
RF Input Impedance of Mixer
Ω 31 -j103
P1dBMIX 1 dB Compression (refer to input), Input matched
dBm
-25
PCGMIX Power Conversion Gain
dB 21
NFMIX Noise Figure of Mixer (SSB), Input matched
dB
9.5
ALO-IF
LO Leakage to IF Pins, PLO = -10 dBm
dBm
-40
ALO-RF LO Leakage to RF Input Pins, PLO = -10 dBm
dBm
-48
ZMIXout RF Output Impedance of Mixer
+152 - j9
PLL
ICPOH
PLL Charge Pump High Side Current @ VCPout = VCC/2
mA
1
ICPOL
PLL Charge Pump Low Side Current @ VCPout = VCC/2
mA
-1
fPD Phase Comparison Frequency
MHz
8.184
IF Downconverter Block (f1stIFin = 61.38 MHz, f2ndLOin = 65.472 MHz, f2ndIF output = 4.092 MHz, ZS = 2kΩ, ZL = 2 kΩ)
NF2ndMIX Noise Figure of 2nd IF Mixer (SSB), (ZS = 50Ω)
dB
12
GV2ndMIX Voltage Gain of 2nd Mixer/Amplifier, P1stIF = -50 dBm
dB
47
VGC Gain Control Voltage (Voltage at maximum gain)
V
0.5
DGC
Gain Control Range, P1stIF = -50 dBm
(Voltage at maximum gain)
dB 20
A2ndLO1stIF 2nd LO Isolation to 1st IF Input Pins, VAGC = 0 V
dB
-70
A2ndLO2ndIF 2nd LO Isolation to 2nd IF Output Pins, VAGC = 0 V
dB
-70
3.2
10
California Eastern Laboratories
1 Page CURRENT BUDGET
SYMBOL
PARAMETER AND CONDITIONS
IC Performance Parameters
VCC Supply Voltage
ICC Total Circuit Current, VCC = 3.0 V, no signal
ICC_PL
Power Down Node Current
ICC_XO
Oscillator Supply Current, (Pin 15 = 0 V, Pin 16 = 3 V)
ICC_RX
Receiver Supply Current, (Pin 15 = 0 V, Pin 16 = 3 V)
Functional Blocks Current Details
ICC_LNA
Supply Current of LNA, RF off
ICC_MIX1
Supply Current of RF Mixer, RF off
ICC_MIX2
Supply Current of IF Mixer, RF off
ICC_IFAMP
Supply Current of IF Amplifier, RF off
ICC_XO
Crystal Oscillator Supply Current
ICC9
PLL Supply Current
ICC_CF
Control Functions Supply Current
VIL Power Down Pin Logic LOW Level
VIH Power Down Pin Logic HIGH Level
τd_PON
Power-on Response Time
UNITS
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
V
V
ms
MIN
2.7
1.8
UPB1007K
TYP MAX
3.0 3.3
25 31
0.15
2.7
22.3
2.6
6.7
3.5
1.1
2.7
6.3
2.1
0.6
3
APPLICATION EXAMPLE
1575.42 MHz
25
8 PD
2
LOOP FILTER
TUNING ELEMENT
REFERENCE FREQ.
3Pages UPB1007K
PIN FUNCTIONS
Pin No.
Symbol
Function and Application
18 REF gnd
Differential oscillator input.
This pin should be grounded via a capacitor.
19 REFin Input pin of the reference frequency
buffer. This pin should be equipped with
an external 16.368 MHz oscillator (e.g.
TCXO).
20 VCC
Supply voltage pin of output charge pump
(Ref Block)
of the oscillator.
21 GND Ground pin of the oscillator, prescaler,
(Ref Block)
phase detector and VCO.
22 2nd IFout
Output pin of 2nd IF amplifier. This pin
output 4.092 MHz clipped sinewave. This
pin should be equipped with external
inverter to adjust level to next stage on
user's system.
23 VCC
2ndIFAMP
Supply voltage pin of 2ndIF amplifier
24 2ndIF bypass Bypass pin of 2nd IF amplifier input. This
pin should be grounded via a capacitor.
25
2ndIFin1
Pin 1 of 2nd IF amplifier input . 2nd IF filter
can be inserted between 25 & 28.
26 2ndIFin2 Pin 2 of 2nd IF amplifier input. This pin
should be grounded via a capacitor.
27
GND
Ground pin of 2nd IF amplifier.
(2ndIF AMP)
28
IF MIXout
Output pin from IF mixer. IF mixer output
signal goes through gain control amplifier
before this emitter follower output port.
Internal Equivalent Circuit
29 VCC (IF MIX) Supply voltage pin of IF mixer, gain control
amplifier.
6 Page | |||
ページ | 合計 : 8 ページ | ||
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PDF ダウンロード | [ UPB1007K データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
UPB1007K | PLL FREQUENCY SYNTHESIZER | ETC |