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PDF UPA1792 Data sheet ( Hoja de datos )
| Número de pieza | UPA1792 | |
| Descripción | SWITCHING N- AND P-CHANNEL POWER MOS FET INDUSTRIAL USE | |
| Fabricantes | NEC | |
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DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ PA1792
SWITCHING
N- AND P-CHANNEL POWER MOS FET
INDUSTRIAL USE
DESCRIPTION
The µPA1792 is N- and P-Channel MOS Field Effect Transistors
designed for Motor Drive application of HDD and so on.
FEATURES
• Low on-resistance
N-Channel RDS(on)1 = 26 mΩ MAX. (VGS = 10 V, ID = 3.4 A)
RDS(on)2 = 36 mΩ MAX. (VGS = 4.5 V, ID = 3.4 A)
RDS(on)3 = 42 mΩ MAX. (VGS = 4.0 V, ID = 3.4 A)
P-Channel RDS(on)1 = 36 mΩ MAX. (VGS = –10 V, ID = –2.9 A)
RDS(on)2 = 54 mΩ MAX. (VGS = –4.5 V, ID = –2.9 A)
RDS(on)3 = 65 mΩ MAX. (VGS = –4.0 V, ID = –2.9 A)
• Low input capacitance
N-Channel Ciss = 760 pF TYP.
P-Channel Ciss = 900 pF TYP.
• Built-in G-S protection diode
• Small and surface mount package (Power SOP8)
ORDERING INFORMATION
PART NUMBER
PACKAGE
µPA1792G
Power SOP8
Gate
PACKAGE DRAWING (Unit : mm)
85
14
5.37 MAX.
N-Channel
1 ; Source 1
2 ; Gate 1
7,8 ; Drain 1
P-Channel
3 ; Source 2
4 ; Gate 2
5,6 ; Drain 2
6.0 ±0.3
4.4
0.8
1.27 0.78 MAX.
0.40
+0.10
–0.05
0.12 M
0.5 ±0.2
0.10
EQUIVALENT CIRCUIT
Drain
Drain
Body
Diode
Gate
Body
Diode
Gate
Protection
Diode
Source
N-Channel
Gate
Protection
Diode
Source
P-Channel
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. G14557EJ1V0DS00 (1st edition)
Date Published July 2000 NS CP(K)
Printed in Japan
©
1999, 2000
1 page  
TYPICAL CHARACTERISTICS (TA = 25°C)
A) N-Channel
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
100
80
60
40
20
0
0 20 40 60 80 100 120 140 160
TA - Ambient Temperature - ˚C
µPA1792
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
2.8
Mounted on ceramic
substrate of
2.4 2000 mm2×1.6 mm
2 unit
2.0
1 unit
1.6
1.2
0.8
0.4
00 20 40 60 80 100 120 140 160
TA - Ambient Temperature - ˚C
FORWARD BIAS SAFE OPERATING AREA
100
10 RD(VS(GonS)=Li1m0itVe)d
ID(DC)
ID(pulse)
Mounted on ceramic
substrate of
2000 mm2×1.6 mm, 1 unit
PW
= 100 µs
1 ms
1
Power
Dissipation
100
Limited
10
ms
ms
TA = 25 ˚C
0.1 Single Pulse
0.1
1
10
VDS - Drain to Source Voltage - V
100
1000
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
100
Rth(ch-A) = 73.5˚C/W
10
1
0.1
0.01100µ
1m
10 m 100 m
Mounted on ceramic
substrate of 2000 mm2 × 1.6 mm
Single Pulse, 1 unit, TA = 25˚C
1 10 100 1000
PW - Pulse Width - s
Data Sheet G14557EJ1V0DS00
5
5 Page 
[MEMO]
µPA1792
Data Sheet G14557EJ1V0DS00
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet UPA1792.PDF ] | |
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