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PDF UPA1721 Data sheet ( Hoja de datos )
| Número de pieza | UPA1721 | |
| Descripción | SWITCHING N-CHANNEL POWER MOS FET INDUSTRIAL USE | |
| Fabricantes | NEC | |
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DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ PA1721
SWITCHING
N-CHANNEL POWER MOS FET
INDUSTRIAL USE
DESCRIPTION
The µPA1721 is N-Channel MOS Field Effect
Transistor designed for DC/DC converters and power
management applications of notebook computers.
FEATURES
• Low on-resistance
RDS(on)1 = 10.5 mΩ MAX. (VGS = 10 V, ID = 5.0 A)
RDS(on)2 = 14.0 mΩ MAX. (VGS = 4.5 V, ID = 5.0 A)
RDS(on)3 = 17.0 mΩ MAX. (VGS = 4.0 V, ID = 5.0 A)
• Low Ciss: Ciss = 2200 pF TYP.
• Built-in G-S protection diode
• Small and surface mount package (Power SOP8)
ORDERING INFORMATION
PART NUMBER
PACKAGE
µPA1721G
Power SOP8
PACKAGE DRAWING (Unit : mm)
85
1,2,3 ; Source
4 ; Gate
5,6,7,8 ; Drain
14
5.37 MAX.
6.0 ±0.3
4.4
0.8
1.27 0.78 MAX.
0.40
+0.10
–0.05
0.12 M
0.5 ±0.2
0.10
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)
Drain to Source Voltage (VGS = 0 V)
VDSS 30 V
Gate to Source Voltage (VDS = 0 V)
VGSS ±20 V
Drain Current (DC)
ID(DC)
±10
A
Drain Current (pulse) Note1
ID(pulse)
±40
A
Total Power Dissipation (TA = 25°C) Note2
PT
2.0 W
Channel Temperature
Tch 150 °C
Storage Temperature
Tstg –55 to +150 °C
EQUIVALENT CIRCUIT
Drain
Gate
Body
Diode
Gate
Protection
Diode
Source
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1 %
• 2. Mounted on ceramic substrate of 1200 mm2 x 2.2 mm
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. G13889EJ1V0DS00 (1st edition)
Date Published November 1999 NS CP(K)
Printed in Japan
The mark 5 shows major revised points.
©
1998,1999
1 page  
µ PA1721
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
20
18 VGS = 4.0 V
16 4.5 V
14
12 10 V
10
8
6
4
2
ID = 5 A
0
−50 0 50 100 150
Tch - Channel Temperature - ˚C
10000
1000
100
CAPACITANCE vs. DRAIN TO
SOURCE VOLTAGE
VGS = 0 V
f = 1 MHz
Ciss
Coss
Crss
10
0.1
1 10
VDS - Drain to Source Voltage - V
100
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
40 16
14
30 12
VDD = 24 V
20
15 V
6V
10
VGS
8
6
10 4
2
VDS
00
0 5 10 15 20 35 40 45 50
QG - Gate Charge - nC
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
Pulsed
100
10 VGS = 10 V
1
0V
0.1
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VSD - Source to Drain Voltage - V
1 000
REVERSE RECOVERY TIME vs.
DRAIN CURRENT
di/dt = 100A /µs
VGS = 0 V
100
10
1
0.1
1 10
ID - Drain Current - A
100
Data Sheet G13889EJ1V0DS00
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet UPA1721.PDF ] | |
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