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UPA104B PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 UPA104B
部品説明 HIGH FREQUENCY NPN TRANSISTOR ARRAY
メーカ NEC
ロゴ NEC ロゴ 



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UPA104B Datasheet, UPA104B PDF,ピン配置, 機能
DATA SHEET
COMPOUND TRANSISTOR
µPA104
HIGH FREQUENCY NPN TRANSISTOR ARRAY
FEATURES
9 GHz CONFIGURABLE TRANSISTOR BASED OR/NOR CIRCUITRY
OUTSTANDING hFE LINEARITY
TWO PACKAGE OPTIONS:
µPA104B: Studded ceramic package provides superior thermal dissipation
µPA104G: Reduced circuit size due to 14-pin plastic SOP package for surface mounting
EXCELLENT FOR ANALOG ADDITIONS & FORMATION OF 2-INPUT OR/NOR GATES
DESCRIPTION AND APPLICATIONS
The µPA104 is a user-configurable, Si bipolar transistor array for formation of high speed OR/NOR gates. Its
internal transistor configuration and external connection options allow the user considerable flexibility in its
application. Its high gain bandwidth product (fT = 9 GHz) make it applicable for electro-optical, signal processing,
cellular telephone systems, instrumentation, and high speed gigabit logic circuits.
ORDERING INFORMATION
PART NUMBER
PACKAGE
µPA104B-E1
14-pin ceramic package
µPA104G-E1
14-pin plastic SOP (225 mil)
ABSOLUTE MAXIMUM RATINGS (TA = +25 °C)
SYMBOLS
PARAMETERS
UNITS RATINGS
VCBO*
Collector to Base Voltage V
15
VCEO*
Collector to Emitter Voltage
V
6
VEBO*
Emitter to Base Voltage
V
2.5
IC* Collector Current
mA 40
PT Power Dissipation
µPA104B mW
µPA104G mW
650
350
TJ Junction Temperature
µPA104B °C
µPA104G °C
200
125
TSTG
Storage Temperature
µPA104B °C –55 to +200
µPA104G °C –55 to +125
* Absolute maximum ratings for each transistor.
Caution electro-static sensitive devices
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. P10709EJ2V0DS00 (2nd edition)
Date Published October 1999 N CP(K)
Printed in Japan
The mark shows major revised points.
©
1995, 1999

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