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UMA1015AM の電気的特性と機能

UMA1015AMのメーカーはNXP Semiconductorsです、この部品の機能は「Low-power dual frequency synthesizer for radio communications」です。


製品の詳細 ( Datasheet PDF )

部品番号 UMA1015AM
部品説明 Low-power dual frequency synthesizer for radio communications
メーカ NXP Semiconductors
ロゴ NXP Semiconductors ロゴ 




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UMA1015AM Datasheet, UMA1015AM PDF,ピン配置, 機能
INTEGRATED CIRCUITS
DATA SHEET
UMA1015AM
Low-power dual frequency
synthesizer for radio
communications
Product specification
Supersedes data of 1997 Jun 10
File under Integrated Circuits, IC17
1997 Sep 03

1 Page





UMA1015AM pdf, ピン配列
Philips Semiconductors
Low-power dual frequency synthesizer
for radio communications
Product specification
UMA1015AM
ORDERING INFORMATION
TYPE NUMBER
UMA1015AM
NAME
SSOP20
PACKAGE
DESCRIPTION
plastic shrink small outline package; 20 leads; body width 4.4 mm
BLOCK DIAGRAM
VERSION
SOT266-1
handbook, full pagewidth
CLK
DATA
11
12
4-BIT SHIFT
REGISTER
13
E
ADDRESS
DECODER
6
RFA
5
HPD
fXTALO
fXTALIN
10
8
15
RFB
1997 Sep 03
VDD1
4
VDD2
14
DGND
7
AGND
16
ISET
20
VCC
18
17-BIT SHIFT REGISTER
CONTROL LATCH
power OOL current port
down select ratio bits
LATCH
MAIN DIVIDER
TOOL A
RFA/64
SYNTHESIZER A
PUMP
BIAS
VOLTAGE
DOUBLER
VDB enable
RF/64
PHASE
DETECTOR
3
CPA
LOCK
DETECTOR
phase
error
LATCH
REFERENCE DIVIDER
DIV
BY 2
UMA1015AM
SR
SYNTHESIZER B
LATCH
MAIN DIVIDER
TOOL B
RFB/64
TOOL A
TOOL B
LOCK
SELECT
19
P0/OOL
1
P1
2
P2
9
P3
LOCK
DETECTOR
phase
error
PHASE
DETECTOR
17
CPB
MGG523
Fig.1 Block diagram.
3


3Pages


UMA1015AM 電子部品, 半導体
Table 2 Bit allocation
FIRST
REGISTER BIT ALLOCATION
p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14
dt16 dt15 dt14 dt13 dt12
DATA FIELD
dt4 dt3
X X VDON PO OLA OLB CRA CRB X X sPDA sPDB P3 P2
MA16
SYNTHESIZER A MAIN DIVIDER COEFFICIENT
0 0 0 0 SR R11
REFERENCE DIVIDER COEFFICIENT
MB16
SYNTHESIZER B MAIN DIVIDER COEFFICIENT
RESERVED FOR TEST(1)
0 00 00 0 0 0 0 0 0 0 0 0
p15 p16
dt2 dt1
P1 X
sPBF 0
LAST
p17 p18 p19 p20 p21
dt0 ADDRESS
X
000
1
MA0 0 1 0
0
R0 0 1 0 1
MB0 0 1 1
0
000
0
0
100
0
Note
1. The test register should not be programmed with any other values except all zeros for normal operation.
Table 3 Bit allocation description
SYMBOL
sPDA, sPDB
sPBF
P3, P2, P1 and P0
VDON
OLA, OLB
CRA, CRB
SR
DESCRIPTION
software power-down for synthesizers A and B (0 = power-down)
software power-on for fxtal buffer (1 = buffer on)
bits output to pins 1, 2, 9 and 19 (1 = high impedance)
voltage doubler enable (1 = doubler enabled)
out-of-lock select; selects signal output to pin 19 (see Table 4)
charge pump A/B current to ISET ratio select (see Table 5)
reference frequency ratio select (see Table 6)
Table 4 Out-of-lock select
OLA
0
0
1
1
OLB
0
1
0
1
P0
lock status of loop B; OOLB
lock status of loop A; OOLA
logic OR function of loops A and B
OUTPUT AT PIN 19

6 Page



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部品番号部品説明メーカ
UMA1015AM

Low-power dual frequency synthesizer for radio communications

NXP Semiconductors
NXP Semiconductors


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