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PCA5007H の電気的特性と機能

PCA5007HのメーカーはNXP Semiconductorsです、この部品の機能は「Pager baseband controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 PCA5007H
部品説明 Pager baseband controller
メーカ NXP Semiconductors
ロゴ NXP Semiconductors ロゴ 




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PCA5007H Datasheet, PCA5007H PDF,ピン配置, 機能
INTEGRATED CIRCUITS
DATA SHEET
PCA5007
Pager baseband controller
Product specification
File under Integrated Circuits, IC17
1998 Oct 07

1 Page





PCA5007H pdf, ピン配列
Philips Semiconductors
Pager baseband controller
Product specification
PCA5007
1 FEATURES
Operating temperature from: 10 to +55 °C
Supply voltage range with on-chip DC/DC converter:
0.9 to 1.6 V
Low operating and standby current consumption
On-chip DC/DC converter generates the supply voltage
for the PCA5007 and external circuitry from a single cell
battery
Battery low detector
Low electromagnetic noise emission
Full static asynchronous 80C51 CPU (8-bit CPU)
Recovery from lowest power standby Idle mode to full
speed operation within microseconds
20 kbytes of One-Time Programmable (OTP) memory
and 1-kbyte of RAM on-chip
27 general purpose I/O port lines (4 ports with interrupt
possibility)
15 different interrupt sources with selectable priority
2 standard timer/event counters T0 and T1
I2C-bus serial port (single 100 kHz master transmitter
and receiver)
Subset of standard UART serial port (8 and 9-bit
transmission at 4800/9600 bits/s)
76.8 kHz crystal oscillator reference with digital clock
correction for real time and paging protocol
Real-Time Clock (RTC)
Receiver and synthesizer control
– Receiver control by software through general
purpose I/Os
– Synthesizer control by software through general
purpose I/Os
– 6-bit DAC for AFC to the receiver local oscillator
– Dedicated protocol timer.
Decoding of paging data
– POCSAG or APOC phase 1, advanced high speed
paging protocols are also supported
– Supported data rates: 1200, 1600, 2400 and 3200
symbols/s using a 76.8 kHz crystal oscillator
– Demodulation of Zero-IF I and Q 4 or 2 level FSK
input or direct data input
– Noise filtering of data input and symbol clock
reconstruction
– De-interleaving, error checking and correction, sync
word detection address recognition, buffering and
more is done in software
– All user functions (keypad interface, alerter control,
display, etc.) are implemented in software.
Musical tone generator for beeper, controlled by the
microcontroller
Watchdog timer
48-pin LQFP package.
2 ORDERING INFORMATION
TYPE
NUMBER(1)
PRODUCT TYPE
PCA5007H/XXX pre-programmed OTP
NAME
LQFP48
PACKAGE
DESCRIPTION
plastic low profile quad flat package; 48 leads;
body 7 × 7 × 1.4 mm
VERSION
SOT313-2
Note
1. Please refer to the Order Entry Form (OEF) for this device for the full type number to use when ordering. This type
number will also specify the required OTP code.
1998 Oct 07
3


3Pages


PCA5007H 電子部品, 半導体
Philips Semiconductors
Pager baseband controller
Product specification
PCA5007
5 PINNING
SYMBOL
P3.4 and P3.5
AT
P2.0 to P2.7
P0.0 to P0.4
VDDA
AFCOUT
I(D1)
Q(D0)
VSSA
P0.5 to P0.7
P1.0 to P1.2
P1.3
PIN
1 and 2
3
4 to 11
12 to 16
17
18
19
20
21
22 to 24
25 to 27
28
TYPE
DESCRIPTION
I/O Port 3: P3.4 and P3.5 are configured as push-pull output only (option 3R; see
Section 6.6). Using the software input commands or the secondary port
function is possible by driving the port 3 output lines accordingly:
P3.4 secondary function: T0 (counter input for T0)
P3.5 secondary function: T1 (counter input for T1)
O Beeper high volume control output. Used to drive external bipolar transistor.
I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups (option 1S;
see Section 6.6.3). As inputs, port 2 pins that are externally pulled LOW will
source current because of the internal pull-ups. (see Chapter “DC
characteristics”: Ipu). Port 2 emits the high-order address byte during fetches
from external program memory. In this application, it uses strong internal
pull-ups when emitting logic 1s. Port 2 is also used to control the parallel
programming mode of the on-chip OTP.
I/O Port 0: Port 0 is a bidirectional I/O port with internal pull-ups (option 1S; see
Section 6.6.3). Port 0 pins that have logic 1s written to them are pulled HIGH by
the internal pull-ups and can be used as inputs. Port 0 is also the multiplexed
low-order address and data bus during access to external program and data
memory. In this application, it uses strong internal pull-ups when emitting 1s.
Port 0 also outputs the code bytes during OTP programming verification.
S supply voltage for the analog parts of the PCA5007 and the
receiver/synthesizer control signals (Port 0 pins)
O Buffered analog output of DAC for automatic receiver frequency control.
A voltage proportional to the offset of the receiver frequency can be generated.
Can be enabled/disabled by software.
I input from receiver: may be demodulated NRZ signal or Zero-IF. In phase
limited signal
I input from receiver: may be demodulated NRZ signal or Zero-IF, Quadrature
limited signal.
S ground signal reference (for the analog parts) (connected to substrate)
I/O Port 0: Port 0 is a bidirectional I/O port with internal pull-ups (option 1R,1R and
1S; see Section 6.6.3). Port 0 pins that have logic 1s written to them are pulled
HIGH by the internal pull-ups and can be used as inputs. Port 0 is also the
multiplexed low-order address and data bus during access to external program
and data memory. In this application, it uses strong internal pull-ups when
emitting 1s. Port 0 also outputs the code bytes during OTP programming
verification.
I/O Port 1: Port 1 is an 8-bit quasi bidirectional I/O port with internal pull-ups.
Port 1 pins that have logic 1s written to them are pulled HIGH by the internal
pull-ups and can be used as inputs. As inputs, port 1 pins that are externally
pulled LOW will source current because of the internal pull-ups (see
Chapter “DC characteristics”: Ipu). P1.0 to P1.2 have external interrupts INT2 to
INT4 assigned.
I/O If the UART is disabled (ENS1 in S1CON.4 = 0) then P1.3 can be used as
general purpose P1 port pin. If the UART function is required, then a logic 1
must be written to P1.3. This I/O then becomes the RXD/data line of the UART.
1998 Oct 07
6

6 Page



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部品番号部品説明メーカ
PCA5007

Pager baseband controller

NXP Semiconductors
NXP Semiconductors
PCA5007H

Pager baseband controller

NXP Semiconductors
NXP Semiconductors


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