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PDF IDT82V2084 Data sheet ( Hoja de datos )
| Número de pieza | IDT82V2084 | |
| Descripción | QUAD CHANNEL T1/E1/J1 LONG HAUL/ SHORT HAUL LINE INTERFACE UNIT | |
| Fabricantes | Integrated Device | |
| Logotipo |  |
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QUAD CHANNEL T1/E1/J1 LONG HAUL/
SHORT HAUL LINE INTERFACE UNIT
IDT82V2084
FEATURES:
• Four channel T1/E1/J1 long haul/short haul line interfaces
- Active level of transmit data (TDATA) and receive data (RDATA)
• Supports HPS (Hitless Protection Switching) for 1+1 protection
- Receiver or transmitter power down
without external relays
- High impedance setting for line drivers
• Receiver sensitivity exceeds -36 dB@772KHz and -43 dB@1024
- PRBS (Pseudo Random Bit Sequence) generation and detection
KHz with 215-1 PRBS polynomials for E1
• Programmable T1/E1/J1 switchability allowing one bill of ma-
- QRSS (Quasi Random Sequence Signals) generation and detection
terial for any line condition
• Single 3.3 V power supply with 5 V tolerance on digital interfaces
• Meets or exceeds specifications in
- ANSI T1.102, T1.403 and T1.408
- ITU I.431, G.703,G.736, G.775 and G.823
- ETSI 300-166, 300-233 and TBR 12/13
- AT&T Pub 62411
• Per channel software selectable on:
- Wave-shapingtemplatesforshorthaulandlonghaulLBO(LineBuild
Out)
- Line terminating impedance (T1:100 Ω, J1:110 Ω, E1:75 Ω/120 Ω)
- Adjustment of arbitrary pulse shape
- JA (Jitter Attenuator) position (receive path or transmit path)
- Single rail/dual rail system interfaces
- B8ZS/HDB3/AMI line encoding/decoding
- Active edge of transmit clock (TCLK) and receive clock (RCLK)
•
•
•
•
•
•
•
•
with 220-1 QRSS polynomials for T1/J1
- 16-bit BPV (Bipolar Pulse Violation)/Excess Zero/PRBS or QRSS
error counter
- Analog loopback, Digital loopback, Remote loopback and Inband
loopback
Per channel cable attenuation indication
Adaptive receive sensitivity
Non-intrusive monitoring per ITU G.772 specification
Short circuit protection for line drivers
LOS (Loss Of Signal) & AIS (Alarm Indication Signal) detection
JTAG interface
Supports serial control interface, Motorola and Intel Non-Multi-
plexed interfaces
Package:
IDT82V2084: 128-pin TQFP
DESCRIPTION:
The IDT82V2084 can be configured as a quad T1, quad E1 or quad J1
Line Interface Unit. In receive path, an Adaptive Equalizer is integrated to
removethedistortion introduced bythecableattenuation.TheIDT82V2084
also performs clock/data recovery, AMI/B8ZS/HDB3 line decoding and
detects and reports the LOS conditions. In transmit path, there is an AMI/
B8ZS/HDB3 encoder, Waveform Shaper and LBOs. There is one Jitter
Attenuator for each channel, which can be placed in either the receive path
or the transmit path. The Jitter Attenuator can also be disabled. The
IDT82V2084 supports both Single Rail and Dual Rail system interfaces and
both serial and parallel control interfaces. To facilitate the network mainte-
nance, a PRBS/QRSS generation/detection circuit is integrated in each
channel, and different types of loopbacks can be set on a per channel basis.
Four different kinds of line terminating impedance, 75Ω, 100 Ω, 110 Ω and
120 Ω are selectable on a per channel basis. The chip also provides driver
short-circuit protection and supports JTAG boundary scanning.
The IDT82V2084 can be used in SDH/SONET, LAN, WAN, Routers,
Wireless Base Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay
Access Devices, CSU/DSU equipment, etc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGES
2003 Integrated Device Technology, Inc. All rights reserved.
1
July 2004
DSC-6221/5
1 page  
QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
LIST OF TABLES
INDUSTRIAL
TEMPERATURE RANGES
Table-1
Table-2
Table-3
Table-4
Table-5
Table-6
Table-7
Table-8
Table-9
Table-10
Table-11
Table-12
Table-13
Table-14
Table-15
Table-16
Table-17
Table-18
Table-19
Table-20
Table-21
Table-22
Table-23
Table-24
Table-25
Table-26
Table-27
Table-28
Table-29
Table-30
Table-31
Table-32
Table-33
Table-34
Table-35
Table-36
Table-37
Table-38
Table-39
Table-40
Pin Description ................................................................................................................ 9
Transmit Waveform Value For E1 75 Ω ........................................................................ 16
Transmit Waveform Value For E1 120 Ω ...................................................................... 16
Transmit Waveform Value For T1 0~133 ft................................................................... 16
Transmit Waveform Value For T1 133~266 ft............................................................... 16
Transmit Waveform Value For T1 266~399 ft............................................................... 17
Transmit Waveform Value For T1 399~533 ft............................................................... 17
Transmit Waveform Value For T1 533~655 ft............................................................... 17
Transmit Waveform Value For J1 0~655 ft ................................................................... 17
Transmit Waveform Value For DS1 0 dB LBO.............................................................. 18
Transmit Waveform Value For DS1 -7.5 dB LBO ......................................................... 18
Transmit Waveform Value For DS1 -15.0 dB LBO ....................................................... 18
Transmit Waveform Value For DS1 -22.5 dB LBO ....................................................... 18
Impedance Matching for Transmitter ............................................................................ 19
Impedance Matching for Receiver ................................................................................ 20
Criteria of Starting Speed Adjustment........................................................................... 23
LOS Declare and Clear Criteria for Short Haul Mode ................................................... 24
LOS Declare and Clear Criteria for Long Haul Mode.................................................... 25
AIS Condition ................................................................................................................ 25
Criteria for Setting/Clearing the PRBS_S Bit ................................................................ 26
EXZ Definition ............................................................................................................... 29
Interrupt Event............................................................................................................... 33
Global Register List and Map........................................................................................ 34
Per Channel Register List and Map .............................................................................. 35
ID: Chip Revision Register ............................................................................................ 36
RST: Reset Register ..................................................................................................... 36
GCF0: Global Configuration Register 0 ........................................................................ 36
GCF1: Global Configuration Register 1 ........................................................................ 37
INTCH: Interrupt Channel Indication Register............................................................... 37
JACF: Jitter Attenuator Configuration Register ............................................................. 37
TCF0: Transmitter Configuration Register 0 ................................................................. 38
TCF1: Transmitter Configuration Register 1 ................................................................. 38
TCF2: Transmitter Configuration Register 2 ................................................................. 39
TCF3: Transmitter Configuration Register 3 ................................................................. 39
TCF4: Transmitter Configuration Register 4 ................................................................. 39
RCF0: Receiver Configuration Register 0..................................................................... 40
RCF1: Receiver Configuration Register 1..................................................................... 41
RCF2: Receiver Configuration Register 2..................................................................... 42
MAINT0: Maintenance Function Control Register 0...................................................... 42
MAINT1: Maintenance Function Control Register 1...................................................... 43
5
5 Page 
QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL
TEMPERATURE RANGES
Table-1 Pin Description (Continued)
Name
Type TQFP128
Description
INT/MOT Input
6 INT/MOT: Intel or Motorola Microcontroller Interface Select
In microcontroller mode, the parallel microcontroller interface is configured for Motorola compatible microcontrollers when this
pin is low, or for Intel compatible microcontrollers when this pin is high.
CS
Input
32 CS: Chip Select
In microcontroller mode, this pin is asserted low by the microcontroller to enable microcontroller interface. For each read or write
operation, this pin must be changed from high to low, and will remain low until the operation is over.
SCLK
Input
33 SCLK: Shift Clock
In serial microcontroller mode, signal on this pin is the shift clock for the serial interface. Configuration data on pin SDI is sampled
on the rising edges of SCLK. Configuration and status data on pin SDO is clocked out of the device on the rising edges of SCLK
if pin SCLKE is low, or on the falling edges of SCLK if pin SCLKE is high.
DS/RD
Input
34 DS: Data Strobe
In parallel Motorola microcontroller interface mode, signal on this pin is the data strobe of the parallel interface. During a write
operation (R/W =0), data on D[7:0] is sampled into the device. During a read operation (R/W =1), data is output to D[7:0] from
the device.
SDI/R/W/WR Input
RD: Read Operation
In parallel Intel microcontroller interface mode, this pin is asserted low by the microcontroller to initiate a read cycle. Data is out-
put to D[7:0] from the device during a read operation.
35 SDI: Serial Data Input
In serial microcontroller mode, data is input on this pin. Input data is sampled on the rising edges of SCLK.
R/W: Read/Write Select
In parallel Motorola microcontroller interface mode, this pin is low for write operation and high for read operation.
WR: Write Operation
In parallel Intel microcontroller interface mode, this pin is asserted low by the microcontroller to initiate a write cycle. Data on
D[7:0] is sampled into the device during a write operation.
SDO Output 36 SDO: Serial Data Output
In serial microcontroller mode, signal on this pin is the output data of the serial interface. Configuration and status data on pin
SDO is clocked out of the device on the active edge of SCLK.
INT Output 37 INT: Interrupt Request
This pin outputs the general interrupt request for all interrupt sources. If INTM_GLB bit (GCF0, 40H) is set to ‘1’ all the interrupt
sources will be masked. And these interrupt sources also can be masked individually via registers (INTM0, 11H) and (INTM1,
12H). Interrupt status is reported via byte INT_CH (INTCH, 80H), registers (INTS0, 16H) and (INTS1, 17H).
Output characteristics of this pin can be defined to be push-pull (active high or low) or be open-drain (active low) by bits
INT_PIN[1:0] (GCF0, 40H).
D7 I / O 14 Dn: Data Bus 7~0
D6 Tri-state 15 These pins function as a bi-directional data bus of the microcontroller interface.
D5 16
D4 17
D3 18
D2 19
D1 20
D0 21
A7
Input
24 An: Address Bus 7~0
A6 25 These pins function as an address bus of the microcontroller interface.
A5 26
A4 27
A3 28
A2 29
A1 30
A0 31
RST
Input
38 RST: Hardware Reset
The chip is reset if a low signal is applied on this pin for more than 100ns. All the drivers output are in high-impedance state,
all the internal flip-flops are reset and all the registers are initialized to their default values.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IDT82V2084.PDF ] | |
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