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PDF RTL8308B Data sheet ( Hoja de datos )
| Número de pieza | RTL8308B | |
| Descripción | REALTEK SINGLE CHIP 8-PORT 10/100 ETHERNET SWITCH CONTROLLER WITH EMBEDDED MEMORY | |
| Fabricantes | ETC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de RTL8308B (archivo pdf) en la parte inferior de esta página. Total 28 Páginas | ||
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REALTEK SINGLE CHIP
8-PORT 10/100 ETHERNET
SWITCH CONTROLLER
WITH EMBEDDED MEMORY
RTL8308B
RTL8308B
1. Features ................................................................2
2. General Description ............................................3
3. Block Diagram .....................................................4
4. Pin Assignments...................................................5
5. Pin Description ....................................................6
5.1 RMII Interface ................................................6
5.2 Serial EEPROM 24LC02 Interface.................7
5.3 System Pins.....................................................7
5.4 Mode Pins (Reset-Read) .................................7
5.5 LED Pin ..........................................................8
5.6 Test Pin............................................................8
5.7 Power & Ground Pins .....................................8
6. Functional Description........................................9
6.1 Reset................................................................9
6.2 Network Interface ...........................................9
6.2.1 Medium Access Control ..........................9
6.2.2 Auto Negotiation....................................10
6.2.3 MII Interface ..........................................10
6.2.4 RMII interface .......................................10
6.2.5 Illegal Frames ........................................11
6.3 EEPROM Interface .......................................11
6.4 Serial Management Interface MDC/MDIO ..12
6.5 Reversible PHYAD Order.............................13
6.6 Address Search and Learning .......................13
6.7 Address Hashing Mode.................................14
6.8 Address Direct Mapping Mode.....................14
6.9 Frame Filtering..............................................14
6.10 Back off Algorithm .................................... 15
6.11 Inter-Frame Gap ......................................... 15
6.12 Buffer Management.................................... 15
6.13 Buffer Manager .......................................... 15
6.14 Data Reception ........................................... 16
6.15 Data Forwarding......................................... 16
6.16 Flow Control .............................................. 17
6.17 Cut Through ............................................... 17
6.18 Broadcast Storm Filtering Control ............. 17
6.19 Loop Detection........................................... 18
6.20 Head-Of-Line Blocking.............................. 18
6.21 24LC02 Interface........................................ 18
6.22 24LC02 Device Operation ......................... 19
6.23 Testing ........................................................ 21
6.23.1 External SRAM Test ........................... 21
6.23.2 Production Testing .............................. 21
6.23.3 Loopback............................................. 21
7. 24LC02 Serial EEPROM Format ................... 22
8. Electrical Characteristics................................. 23
8.1 Temperature Limit Ratings........................... 23
8.2 DC Characteristics........................................ 23
8.3 AC Characteristics........................................ 23
8.3.1 Reset and Clock Timing........................ 23
8.3.2 RMII Timing ......................................... 24
8.3.3 PHY Management Timing .................... 25
8.3.4 Serial EEPROM 24LC02 Timing ......... 26
9. Mechanical Information................................... 27
2002/01/23
1 Rev. 2.0
1 page  
4. Pin Assignments
84 NC
85 VCC
86 TXE[G]
87 TXD0[G]
88 TXD1[G]
89 CRSDV[G]
90 RXD0[G]
91 RXD1[G]
92 TXE[H]
93 TXD0[H]
94 TXD1[H]
95 VCC
96 CRSDVH]
97 RXD0[H]
98 RXD1[H]
99 NC
100 NC
101 GND
102 NC
103 VCC
104 NC
105 GND
106 TEST
107 ENBKPRS
108 EnBrdCtrl
109 VCC
110 NC
111 GND
112 ENFCTRL
113 VCC
114 NC
115 GND
116 GND
117 ENCUTHR
118 NC
119 SYSCLK
120 NC
121 SCLK
122 SDA
123 NC
124 VCC
125 NC
126 GND
127 NC
128 VCC
1 NC
2 NC
3 NC
4 NC
5 NC
6 GND
7 TXE[A]
8 TXD0[A]
9 TXD1[A]
10 CRSDV[A]
11 RXD0[A]
12 RXD1[A]
13 TXE[B]
14 TXD0[B]
15 TXD1[B]
16 VCC
17 VCC
18 CRSDV[B]
19 RXD0[B]
RTL8308B
RTL8308B
83 GND
82 GND
81 RXD1[F]
80 RXD0[F]
79 CRSDV[F]
78 TXD1[F]
77 TXD0[F]
76 TXE[F]
75 GND
74 RXD1[E]
73 RXD0[E]
72 CRSDV[E]
71 GND
70 TXD1[E]
69 TXD0[E]
68 TXE[E]
67 NC
66 VCC
65 NC
64 GND
63 RXD1[D]
62 RXD0[D]
61 CRSDV[D]
60 TXD1[D]
59 TXD0[D]
58 TXE[D]
57 NC
56 NC
55 NC
54 LOOPLED#
53 RST#
52 VCC
51 VCC
50 NC
49 GND
48 GND
47 REFCLK
46 NC
45 NC
44 MDIO
43 MDC
42 NC
41 NC
40 VCC
39 VCC
38 NC
37 NC
36 GND
35 GND
34 GND
33 NC
32 NC
31 RXD1[C]
30 GND
29 RXD0[C]
28 CRSDV[C]
27 TXD1[C]
26 TXD0[C]
25 VCC
24 TXE[C]
23 GND
22 GND
21 GND
20 RXD1[B]
2002/01/23
5 Rev. 2.0
5 Page 
RTL8308B
6.2.5 Illegal Frames
During the receiving process, the MAC will monitor the length of the received frame. Illegal frames such as a bad
CRC packet, runt packet (less than 64 bytes) or oversized packet (greater than 1536) will be discarded.
If the carrier sense (CRS) signal in the RMII interface is asserted and RXD[1:0] at the beginning of the packet is
‘10’, the port is considered to have a false carrier event. Normal carrier has a preamble value of ‘01’. The false
carrier event is recorded for the MIB counter.
The RTL8308B can handle frames up to 1536 bytes. All frames longer than 1536 byte will be discarded. If the port
continues to receive data after the 1536th byte, the port’s data will be filtered. If the port is in half duplex mode, the
port will no longer be able to transmit or receive data during the long packet reception.
6.3 EEPROM Interface
The serial EEPROM interface is designed to load information required by various optional functions. The interface
implements the SDA signal and it is directly compatible with the 93C46 device. The controller reads, in serial
format, in the first 272 bits (seventeen 16-bit words) out of the EEPROM and stores them in registers. Because the
information stored in EEPROM is static, this read occurs only on power-up. The serial EEPROM shifts out the
most significant bit of the word first.
2002/01/23
11 Rev. 2.0
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet RTL8308B.PDF ] | |
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