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RTL8201 の電気的特性と機能

RTL8201のメーカーはETCです、この部品の機能は「REALTEK SINGLE CHIP SINGLE PORT 10/100M FAST ETHERNET PHYCEIVER RTL8201BL」です。


製品の詳細 ( Datasheet PDF )

部品番号 RTL8201
部品説明 REALTEK SINGLE CHIP SINGLE PORT 10/100M FAST ETHERNET PHYCEIVER RTL8201BL
メーカ ETC
ロゴ ETC ロゴ 




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RTL8201 Datasheet, RTL8201 PDF,ピン配置, 機能
RTL8201BL
REALTEK SINGLE CHIP
SINGLE PORT 10/100M
FAST ETHERNET PHYCEIVER
RTL8201BL
1. Features........................................................................... 2
2. General Description ....................................................... 2
3. Block Diagram................................................................ 3
4. Pin Assignments ............................................................. 4
5. Pin Description ............................................................... 5
5.1 100 Mbps MII & PCS Interface ................................ 5
5.2 SNI (Serial Network Interface): 10Mbps only .......... 5
5.3 Clock Interface .......................................................... 6
5.4 100Mbps Network Interface...................................... 6
5.5 Device Configuration Interface ................................. 6
5.6 LED Interface/PHY Address Config......................... 7
5.7 Reset and other pins .................................................. 7
5.8 Power and Ground pins ............................................. 7
6. Register Descriptions ..................................................... 8
6.1 Register 0 Basic Mode Control Register ................... 8
6.2 Register 1 Basic Mode Status Register ..................... 9
6.3. Register 2 PHY Identifier Register 1 ....................... 9
6.4. Register 3 PHY Identifier Register 2 ....................... 9
6.5. Register 4 Auto-negotiation Advertisement
Register(ANAR) ........................................................... 10
6.6 Register 5 Auto-Negotiation Link Partner Ability
Register(ANLPAR) ....................................................... 10
6.7 Register 6 Auto-negotiation Expansion
Register(ANER)............................................................ 11
6.8 Register 16 Nway Setup Register(NSR) ................. 11
6.9 Register 17 Loopback, Bypass, Receiver Error Mask
Register(LBREMR) ...................................................... 12
6.10 Register 18 RX_ER Counter(REC)....................... 12
6.11 Register1910MbpsNetworkInterfaceConfigurationRegister... 12
6.12 Register 20 PHY 1_1 Register .............................. 13
6.13 Register 21 PHY 1_2 Register .............................. 13
6.14 Register 22 PHY 2 Register .................................. 13
6.15 Register 23 Twister_1 Register ............................. 13
6.16 Register 24 Twister_2 Register ............................. 13
6.17 Register 25 Test Register....................................... 13
7. Functional Description ................................................ 14
7.1 MII and Management Interface............................... 14
7.1.1 Data Transition ................................................ 14
7.1.2 Serial Management.......................................... 14
7.2 Auto-negotiation and Parallel Detection ................. 15
7.3 Flow control support ............................................... 16
7.4 Hardware Configuration and Auto-negotiation................. 16
7.5 LED and PHY Address Configuration.................... 17
7.6 Serial Network Interface ......................................... 17
7.7 PowerDown,LinkDown,PowerSaving,andIsolationModes... 18
7.8 Media Interface ....................................................... 18
7.8.1 100Base TX..................................................... 18
7.8.2 100Base-FX Fiber Mode Operation ................ 18
7.8.3 10Base Tx/Rx .................................................. 19
7.9 Repeater Mode Operation ....................................... 19
7.10 Reset, and Transmit Bias(RTSET) ........................ 19
7.11 3.3V power supply and voltage conversion circuit 19
7.12 Far End Fault Indication (FEFI)............................ 20
8. Electrical Characteristics ............................................ 21
8.1 D.C. Characteristics ................................................ 21
8.1.1. Absolute Maximum Ratings........................... 21
8.1.2. Operating Conditions ..................................... 21
8.1.3. Power Dissipation........................................... 21
8.1.4 Supply Voltage: Vcc ........................................ 21
8.2 A.C. Characteristics ................................................ 22
8.2.1 MII Timing of Transmission Cycle ................. 22
8.2.2 MII Timing of Reception Cycle ...................... 23
8.2.3 SNI Timing of Transmission Cycle ................. 24
8.2.4 SNI Timing of Reception Cycle ...................... 25
8.2.5 MDC/MDIO timing......................................... 26
8.2.6 Transmission Without Collision ...................... 26
8.2.7 Reception Without Error ................................. 26
8.3 Crystal and Transformer Specifications .................. 27
8.3.1 Crystal Specifications...................................... 27
8.3.2 Transformer Specifications.............................. 27
9. Mechanical Dimensions............................................... 28
10. Revision History......................................................... 29
2002-03-29
1
Rev.1.2

1 Page





RTL8201 pdf, ピン配列
3. Block Diagram
100M
MII
Interface
SNI
Interface
10/100
half/full
Switch
Logic
5B 4B
Decoder
4B 5B
Encoder
Data
Alignment
Descrambler
Scrambler
10/100M Auto-negotiation
Control Logic
Link pulse
10M
TXC10
TXD10
Manchester coded
waveform
10M Output waveform
shaping
RXC10
RXD10
Data Recovery
Receive low pass filter
RTL8201BL
RXD
RXC 25M
TXD
TXC 25M
TXC 25M
TXD
RXC 25M
RXD
Parrallel
to Serial
TD+
Variable Current
Baseline
wander
Correction
MLT-3
to NRZI
3 Level
Comparator
3 Level
Driver
Peak
Detect
Adaptive
Equalizer
Serial to
Parrallel
ck
data
Slave
PLL
Control
Voltage
Master
PPL
25M
TXO+
TXO -
RXIN+
RXIN-
2002-03-29
3
Rev.1.2


3Pages


RTL8201 電子部品, 半導体
RTL8201BL
5.3 Clock Interface
Symbol
X2
Type
O
Pin No.
47
X1 I 46
Description
25MHz Crystal Output: This pin provides the 25MHz crystal output. It
must be left open when X1 is driven with an external 25MHz oscillator.
25MHz Crystal Input: This pin provides the 25MHz crystal input. If a
25MHz oscillator is used, connect X1 to the oscillator’s output. Refer to
section 8.3 to obtain clock source specifications.
5.4 100Mbps Network Interface
Symbol
TPTX+
TPTX-
Type
O
O
RTSET
I
TPRX+
TPRX-
I
I
Pin No.
34
33
28
31
30
Description
Transmit Output: Differential pair shared by 100Base-TX, 100Base-FX and
10Base-T modes. When configured as 100Base-TX, output is an MLT-3
encoded waveform. When configured as 100Base-FX, the output is
pseudo-ECL level.
Transmit Bias Resistor Connection: This pin should be pulled to GND by
a 5.9K(1%) resistor to define driving current for transmit DAC. The
resistance value may be changed, depending on experimental results of the
RTL8201BL.
Receive Input: Differential pair shared by 100Base-TX, 100Base-FX, and
10Base-T modes.
5.5 Device Configuration Interface
Symbol
ISOLATE
Type
I
RPTR
SPEED
I
LI
DUPLEX
ANE
LI
LI
LDPS
MII/SNIB/
RTT3(test)
I
LI/O
Pin No.
43
40
39
38
37
41
44
Description
Set high to isolate the RTL8201BL from the MAC. This will also isolate the
MDC/MDIO management interface. In this mode, the power consumption is
minimum. This pin can be directly connected to GND or VCC.
Set high to put the RTL8201BL into repeater mode. This pin can be directly
connected to GND or VCC.
This pin is latched to input during a power on or reset condition. Set high to
put the RTL8201BL into 100Mbps operation. This pin can be directly connected
to GND or VCC.
This pin is latched to input during a power on or reset condition. Set high to
enable full duplex. This pin can be directly connected to GND or VCC.
This pin is latched to input during a power on or reset condition. Set high to
enable Auto-negotiation mode, set low to force mode. This pin can be directly
connected to GND or VCC.
Set high to put the RTL8201BL into LDPS mode. This pin can be directly
connected to GND or VCC. Refer to Section 7.7 for more information.
This pin is latched to input during a power on or reset condition. Pull high to
set the RTL8201BL into MII mode operation. Set low for SNI mode. This pin
can be directly connected to GND or VCC. In test mode, this pin is an output pin and
redefined as RTT3
2002-03-29
6
Rev.1.2

6 Page



ページ 合計 : 29 ページ
 
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部品番号部品説明メーカ
RTL8201

REALTEK SINGLE CHIP SINGLE PORT 10/100M FAST ETHERNET PHYCEIVER RTL8201BL

ETC
ETC
RTL8201

SINGLE CHIP SINGLE PORT 10/100MBPS FAST ETHERNET PHYCEIVER

REALTEK
REALTEK
RTL8201BL

SINGLE CHIP SINGLE PORT 10/100M FAST ETHERNET PHYCEIVER

REALTEK
REALTEK
RTL8201BL-LF

SINGLE CHIP SINGLE PORT 10/100M FAST ETHERNET PHYCEIVER

REALTEK
REALTEK


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