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Número de pieza TEA1066T
Descripción Versatile telephone transmission circuit with dialler interface
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INTEGRATED CIRCUITS
DATA SHEET
TEA1066T
Versatile telephone transmission
circuit with dialler interface
Product specification
Supersedes data of September 1990
File under Integrated Circuits, IC03
1996 Apr 04

1 page




TEA1066T pdf
Philips Semiconductors
Versatile telephone transmission circuit
with dialler interface
Product specification
TEA1066T
The voltage regulator adjusts the average voltage on
LN to:
VLN = Vref + ISLPE × R9
or
VLN = Vref + (Iline ICC 0.5 × 103A Ip) × R9
where Vref is an internally generated temperature
compensated reference voltage of 4.2 V and R9 is an
external resistor connected between SLPE and VEE.
The preferred value for R9 is 20 Ω. Changing the value of
R9 will also affect microphone gain, DTMF gain, gain
control characteristics, side-tone level and the maximum
output swing on LN.
Under normal conditions, when ISLPE >> ICC + 0.5 mA + Ip,
the static behaviour of the circuit is that of a 4.2 V regulator
diode with an internal resistance equal to that of R9. In the
audio frequency range, the dynamic impedance is largely
determined by R1 (see Fig.3).
LN
handbook, halfpage
Leq R p
V ref
REG
R1
VCC
and > 3 V, this being the minimum supply voltage for most
CMOS circuits, including voltage drop for an enable diode.
If MUTE is LOW, the available current is further reduced
when the receiving amplifier is driven.
Microphone inputs MICL+, MICH+, MICLand MICH
and amplification adjustment connections GAS1 and
GAS2
The TEA1066T has symmetrical microphone inputs.
The MICL+ and MICLinputs are intended for
low-sensitivity, low-impedance dynamic or magnetic
microphones. The input impedance is 8.2 k(2 × 4.1 k)
and its voltage gain is typically 52 dB. The MICH+ and
MICHinputs are intended for a piezoelectric microphone
or an electret microphone with a built-in FET source
follower. Its input impedance is 40.8 k(2 × 20.4 k) and
its voltage gain is typical 38 dB.
The arrangements with the microphone types mentioned
are shown in Fig.9.
The gain of the microphone amplifier in both types can be
adjusted over a range of ±8 dB to suit the sensitivity of the
transducer used. The gain is proportional to external
resistor R7 connected between GAS1 and GAS2.
An external capacitor C6 of 100 pF between GAS1 and
SLPE is required to ensure stability. A larger value may be
chosen to obtain a first-order low-pass filter. The cut-off
frequency corresponds with the time constant R7 × C6.
V EE
R9
20
C3
4.7 µF
C1
100 µF
MBA454
Rp = 17.5 k
Leq = C3 × R9 × Rp
Fig.3 Equivalent impedance circuit.
The internal reference voltage can be adjusted by means
of an external resistor RVA. This resistor, connected
between LN and REG (pins 1 and 18), will decrease the
internal reference voltage; when connected between REG
and SLPE (pins 18 and 20) it will increase the internal
reference voltage.
Current Ip, available from VCC for supplying peripheral
circuits, depends on external components and on the line
current. Figure 8 shows this current for VCC > 2.2 V
Mute input MUTE
A HIGH level at MUTE enables the DTMF input and
inhibits the microphone inputs and the receiving amplifier;
a LOW level or an open circuit has the reverse effect.
Switching the mute input will cause negligible clicks at the
earpiece outputs and on the line.
Dual-tone multi frequency input DTMF
When the DTMF input is enabled, dialling tones may be
sent onto the line. The voltage gain from DTMF to LN is
typically 25.5 dB and varies with R7 in the same way as
the gain of the microphone amplifier. The signalling tones
can be heard in the earpiece at a low level (confidence
tone).
Receiving amplifier: IR, QR+, QRand GAR
The receiving amplifier has one input IR and two
complementary outputs, a non-inverting output QR+ and
an inverting output QR.
1996 Apr 04
5

5 Page





TEA1066T arduino
Philips Semiconductors
Versatile telephone transmission circuit
with dialler interface
Product specification
TEA1066T
SYMBOL
PARAMETER
CONDITIONS
Vo(rms)
output voltage (RMS value)
Vno(rms)
noise output voltage (RMS value)
Gain adjustment GAR (pin 6)
sine-wave drive; Iline = 15 mA;
Ip = 0 mA; THD = 2%;
R4 = 100 k
single-ended; RL = 150
single-ended; RL = 450
differential; CL = 47 nF;
Rseries = 100 ; f = 3400 Hz
Iline = 15 mA; R4 = 100 kΩ;
pin 13 (IR) open;
psophometrically weighted
(P53 curve)
single-ended; RL = 300
differential; RL = 600
Gv gain variation with R4 connected
between pin 6 and pin 5 receiving
amplifier
MUTE input (pin 16)
VIH
VIL
IMUTE
Gv
Gv
HIGH level input voltage
LOW level input voltage
input current
voltage gain reduction between
MICL+ (pin 9) and MICL(pin 7) to
LN (pin 1)
voltage gain from DTMF to QR+ or
QR
MUTE = HIGH
MUTE = HIGH; R4 = 100 k;
single-ended; RL = 300
Power-down input PD (pin 14)
VIH HIGH level input voltage
VIL LOW level input voltage
IPD input current in power-down
condition
MIN. TYP. MAX. UNIT
0.30 0.38
0.40 0.52
0.80 1.0
V
V
V
50 − µV
100 − µV
8
+8 dB
1.50
−−
5
70
VCC V
0.3 V
10 µA
dB
21 19 17 dB
1.5
−−
5
VCC V
0.3 V
10 µA
1996 Apr 04
11

11 Page







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