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TDA9170 の電気的特性と機能

TDA9170のメーカーはNXP Semiconductorsです、この部品の機能は「YUV picture improvement processor based on histogram modification」です。


製品の詳細 ( Datasheet PDF )

部品番号 TDA9170
部品説明 YUV picture improvement processor based on histogram modification
メーカ NXP Semiconductors
ロゴ NXP Semiconductors ロゴ 




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TDA9170 Datasheet, TDA9170 PDF,ピン配置, 機能
Philips Semiconductors
YUV picture improvement processor based
on histogram modification
Preliminary specification
TDA9170
FEATURES
Picture content dependent non-linear Y and U, V
processing by histogram analysis
Adaptive and variable gamma correction controls
Black and white stretch capabilities
Transparent I2C-bus control
On-chip window generator for valid histogram
measurement and black detection.
GENERAL DESCRIPTION
The TDA9170 is a transparent analog video processor
with a YUV interface. It offers three main luminance
processing functions any combination of which can be
selected.
The luminance transfer is controlled in a non-linear
manner by the distribution (in 5 discrete histogram
sections) of the luminance values measured in a picture.
As a result, the contrast ratio of the most important parts of
the picture will be improved.
Black restoration is available in the event of a set-up in the
luminance signal. A variable gamma function, after the
histogram conversion, offers the possibility of excellent
brightness control.
To maintain a proper colour reproduction, the saturation of
the U and V colour difference signals are controlled as a
function of the actual non-linearity in the luminance
channel.
The TDA9170 concept has maximum flexibility with the
optional on-board I2C-bus (including hardwired address
select) and window control. The supply voltage is 8 V. The
device is mounted in a 32 pin SDIP envelope.
ORDERING INFORMATION
TYPE NUMBER
TDA9170
NAME
SDIP32
PACKAGE
DESCRIPTION
plastic shrink in-line package; 32 leads (400 mil)
VERSION
SOT232-1
October 1994
2

1 Page





TDA9170 pdf, ピン配列
Philips Semiconductors
YUV picture improvement processor based
on histogram modification
PINNING
SYMBOL
DWS
VARGAM
AMPNLA
ADGAM
UIN
Vref
VIN
AGND
VDDA
SC
BOF
YIN
AMPSEL
TAUBP
TAUBL
HM1
HM2
HM3
HM4
HM5
YOUT
TAUHM
n.c.
VDDD
DGND
VOUT
DT
UOUT
TM
SDA
SCL
ADR
PIN DESCRIPTION
1 default window select input
2 variable gamma input
3 amplitude non-linearity input
4 adaptive gamma input
5 colour difference U input
6 reference supply voltage output
(+4 V)
7 colour difference V input
8 analog ground
9 analog supply voltage
10 sandcastle input
11 black offset on/off input
12 luminance input
13 amplitude select input
14 time constant black peak
15 time constant black loop
16 histogram segment memory 1
17 histogram segment memory 2
18 histogram segment memory 3
19 histogram segment memory 4
20 histogram segment memory 5
21 luminance output
22 time constant histogram
measurement loop
23 not connected
24 digital supply voltage (+5 V)
25 digital ground
26 colour difference V output
27 test option
28 colour difference U output
29 test option
30 serial data input/output
(I2C-bus)
31 serial clock input (I2C-bus)
32 address select input (I2C-bus)
Preliminary specification
TDA9170
Fig.2 Pin configuration.
October 1994
4


3Pages


TDA9170 電子部品, 半導体
Philips Semiconductors
YUV picture improvement processor based
on histogram modification
Preliminary specification
TDA9170
Table 1 Slave address.
A6 A5 A4 A3 A2 A1 A0 R/W
1 1 0 1 0 0 ADR X
Table 2 Control function.
CONTROL
FUNCTION
TYPE SUB-ADDRESS(1)
D7
D6
DATA BYTE
D5 D4 D3 D2
Control
REG
00
X X X BON WD2 WD1
User variable
gamma
DAC
01
X X D5 D4 D3 D2
Adaptive gamma DAC
02
X X D5 D4 D3 D2
Non-linear
amplifier
DAC
03
X X D5 D4 D3 D2
Line start stop
REG
04
ST3 ST2 ST1 ST0 SP3 SP2
Field start stop REG 05 ST3 ST2 ST1 ST0 SP3 SP2
Status
REG
XXXXXX
Note
1. Valid sub-addresses: 00 to 05 (HEX); auto-increment mode available for sub-addresses.
D1
AMS
D1
D1
D1
SP1
SP1
X
D0
SLP
D0
D0
D0
SP0
SP0
POR
Table 3 Window select bits (WD1 and WD2).
WD1
0
0
1
WD2
0
1
X
FUNCTION
default window
window by sandcastle blanking
user window
Table 4 Amplitude select bit (AMS).
LOGIC LEVEL
0
1
FUNCTION
0.3 V luminance
1 V luminance
Table 5 Sleep mode bit (SLP).
LOGIC LEVEL
0
1
FUNCTION
sleep
I2C-bus control
Table 6 Black offset compensation enable bit (BON).
LOGIC LEVEL
0
1
disabled
enabled
FUNCTION
October 1994
7

6 Page



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共有リンク

Link :


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