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TP3404V の電気的特性と機能

TP3404VのメーカーはNational Semiconductorです、この部品の機能は「Quad Digital Adapter for Subscriber Loops (QDASL)」です。


製品の詳細 ( Datasheet PDF )

部品番号 TP3404V
部品説明 Quad Digital Adapter for Subscriber Loops (QDASL)
メーカ National Semiconductor
ロゴ National Semiconductor ロゴ 




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TP3404V Datasheet, TP3404V PDF,ピン配置, 機能
PRELIMINARY
July 1994
TP3404
Quad Digital Adapter for Subscriber Loops (QDASL)
General Description
The TP3404 is a combination 4-line transceiver for voice
and data transmission on twisted pair subscriber loops typi-
cally in PBX line card applications It is a companion device
to the TP3401 2 3 DASL single-channel transceivers In
addition to 4 independent transceivers a time-slot assign-
ment circuit is included to support interfacing to the system
backplane
Each QDASL line operates as an ISDN ‘‘U’’ Interface for
short loop applications typically in a PBX environment pro-
viding transmission for 2 B channels and 1 D channel
Full-duplex transmission at 144 kb s is achieved on single
twisted wire pairs using a burst-mode technique (Time Com-
pression Multiplexed) All timing sequences necessary for
loop activation and de-activation are generated on-chip
Alternate Mark Inversion (AMI) line coding is used to ensure
low error rates in the presence of noise with lower emi radia-
tion than other codes such as Biphase (Manchester) On
24 AWG cable the range is at least 1 8 km (6k ft)
Features
4 COMPLETE ISDN PBX 2-WIRE DATA TRANSCEIVERS
INCLUDING
Y Quad 2 B plus D channel interface for PBX ‘‘U’’
interface
Y 144 kb s full-duplex on 1 twisted pair using Burst Mode
Transmission Technique
Y Loop range up to 6 kft ( 24AWG)
Y Alternate Mark Inversion coding with transmit Pulse
Shaping DAC Smoothing Filter and scrambler for low
emi radiation
Y Adaptive line equalizer
Y On-chip timing recovery no external components
Y Programmable Time-Slot Assignment TDM interface for
B channels
Y Separate interface for D channel with Programmable
Sub-Slot Assignment
Y 4 096 MHz master clock
Y 4 loop-back test modes
Y MICROWIRETM compatible serial control interface
Y 5V operation
Y 28-pin PLCC package
Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
MICROWIRETM is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL H 11924
TL H 11924 – 1
RRD-B30M115 Printed in U S A

1 Page





TP3404V pdf, ピン配列
Electrical Characteristics Unless otherwise specified limits printed in BOLD characters are guaranteed for
VCCA e VCCD e 5V g5% TA e 0 C to a70 C Typical characteristics are specified at VDDA e VDDD e 5 0V TA e 25 C All
signals are referenced to GND which is the common of GNDA and GNDD (Continued)
TIMING SPECIFICATIONS (Continued)
Symbol
Parameter
Conditions
DIGITAL INTERFACE TIMING
fBCLK
tWBH
tWBL
tRB
tFB
tHBM
tSFC
tHCF
tSBC
tHCB
tSDC
tHCD
tDCB
tDCBZ
tDCD
tDCZ
BCLK Frequency
Clock Pulse Width High
and Low for BCLK
Rise Time and Fall Time
of BCLK
BCLK Transition to MCLK High or Low
Set up Time FS Valid to BCLK Invalid
Hold Time BCLK Low to FS Invalid
Setup Time BI Valid to BCLK Invalid
Hold Time BCLK Valid to BI Invalid
Setup Time DI Valid to BCLK Low
Hold Time BCLK Low to DI Invalid
Delay Time BCLK High to BO Valid
Delay Time BCLK Low to BO High-Z
Delay Time BCLK High to DO valid
Delay Time BCLK Low to DO High
Impedance
Measured from VIH to VIH
Measured from VIL to VIL
Measured from VIL to VIH
Measured from VIH to VIL
Load e 2 LSTTL a 100 pF
Load e 2 LSTTL a 100 pF
tDCT
Delay Time BCLK High to TSB Low
tZBT
Disable Time BCLK Low to TSB High-Z
MICROWIRE CONTROL INTERFACE TIMING
fCCLK
Frequency of CCLK
tCH Period of CCLK High
Measured from VIH to VIH
tCL Period of CCLK Low
Measured from VIL to VIL
tSSC
Setup Time CS Low to CCLK High
tHCS
Hold Time CCLK High to CS Transition
tSIC Setup Time CI Valid to CCLK High
tHCI Hold Time CCLK High to CI Invalid
tDCO
Delay Time CCLK Low to CO Valid
tDSOZ
Delay Time CS High to CO High-Z
tDCIZ
Delay Time CCLK to INT High-Z
Notes
For the purposes of this specification the following conditions apply
a All input signals are defined as VIL e 0 4V VIH e 2 7V tr k 10 ns tf k 10 ns
b Delay times are measured from the input signal Valid to the output signal Valid
c Setup times are measured from the Data input Valid to the clock input Invalid
d Hold times are measured from the clock signal Valid to the Data input Invalid
Min
70
70
b30
20
40
30
40
30
40
80
40
150
150
50
40
50
20
Typ
4 096
4
30
11
7
Max
41
15
15
30
80
120
80
120
120
120
21
80
80
100
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
3


3Pages


TP3404V 電子部品, 半導体
Functional Description (Continued)
Pulse shaping is obtained by means of a Digital to Analog
Converter followed by a Continuous Smoothing Filter in or-
der to limit RF energy and crosstalk while minimizing Inter-
Symbol Interference (ISI) Figure 2 shows the pulse shape
at the Lo output while a template for the typical power
spectrum transmitted to the line with random data is shown
in Figure 3
Each line-driver output Lo0–Lo3 is designed to drive a
transformer through a capacitor and termination resistor A
1 1 transformer terminated in 100X results in signal ampli-
tude of typically 1 3 Vpk on the line Over-voltage protection
must be included in each interface circuit
LINE RECEIVE SECTIONS
The input of each receive section Li0–Li3 consists of a
continuous anti-alias filter followed by a switched-capacitor
low-pass filter designed to limit the noise bandwidth with
minimum intersymbol interference To correct pulse attenu-
ation and distortion caused by the transmission line an AGC
circuit and first-order equalizer adapt to the received pulse
shape thus restoring a ‘‘flat’’ channel response with maxi-
mum received eye opening over a wide spread of cable
attenuation characteristics
From the equalized output a DPLL (Digital Phase-Locked
Loop) recovers a low-jitter clock for optimum sampling of
the received symbols The MCLK input provides the refer-
ence clock for the DPLL at 4 096 MHz
Following detection of the recovered symbols the received
data is de-scrambled by the same X9 a X5 a 1 polynomial
and presented to the digital system interface circuit
When a transmission line is de-activated a Line-Signal De-
tect Circuit is enabled to detect the presence of incoming
bursts if the far-end starts to activate the loop
FIGURE 2 Typical AMI Waveform at Lo
TL H 11924 – 4
TL H 11924 – 5
FIGURE 3 Typical AMI Transmit Spectrum Measured at LO Output (With RGB e 100 Hz)
6

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
TP3404

Quad Digital Adapter for Subscriber Loops (QDASL)

National Semiconductor
National Semiconductor
TP3404

TP3404 Quad Digital Adapter for Subscriber Loops (QDASL)

Texas Instruments
Texas Instruments
TP3404V

Quad Digital Adapter for Subscriber Loops (QDASL)

National Semiconductor
National Semiconductor


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