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UT8CR512K32-17VCC の電気的特性と機能

UT8CR512K32-17VCCのメーカーはAeroflex Circuit Technologyです、この部品の機能は「UT8CR512K32 16 Megabit SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 UT8CR512K32-17VCC
部品説明 UT8CR512K32 16 Megabit SRAM
メーカ Aeroflex Circuit Technology
ロゴ Aeroflex Circuit Technology ロゴ 




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UT8CR512K32-17VCC Datasheet, UT8CR512K32-17VCC PDF,ピン配置, 機能
Standard Products
UT8CR512K32 16 Megabit SRAM
Advanced Data Sheet
October 2004
www.aeroflex.com/4MSRAM
FEATURES
‰ 17ns maximum access time
‰ Asynchronous operation for compatibility with industry-
standard 512K x 8 SRAMs
‰ CMOS compatible inputs and output levels, three-state
bidirectional data bus
- I/O Voltage 3.3 volts, 1.8 volt core
‰ Radiation performance
- Intrinsic total-dose: 300 Krad(Si)
- SEL Immune >100 MeV-cm2/mg
- LETth (0.25): 53.0 MeV-cm2/mg
- Memory Cell Saturated Cross Section 1.67E-7cm2/bit
- Neutron Fluence: 3.0E14n/cm2
- Dose Rate
- Upset 1.0E9 rad(Si)/sec
- Latchup 1.0E11 rad(Si)/sec
‰ Packaging options:
- 68-lead ceramic quad flatpack (20.238 grams with lead
frame)
‰ Standard Microcircuit Drawing 5962-04227
- QML compliant part
INTRODUCTION
The UT8CR512K32 is a high-performance CMOS static RAM
multi-chip module (MCM), organized as four individual
524,288 words by 8 bit SRAMs with common output enable.
Easy memory expansion is provided by active LOW chip
enables (EN), an active LOW output enable (G), and three-state
drivers. This device has a power-down feature that reduces
power consumption by more than 90% when deselected.
Writing to each memory is accomplished by taking the
corresponding chip enable (En) input LOW and write enable
(Wn) input LOW. Data on the I/O pins is then written into the
location specified on the address pins (A0 through A18). Reading
from the device is accomplished by taking the chip enable (En)
and output enable (G) LOW while forcing write enable (Wn)
HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
The input/output pins are placed in a high impedance state when
the device is deselected (En HIGH), the outputs are disabled (G
HIGH), or during a write operation (En LOW and Wn LOW).
Perform 8, 16, 24 or 32 bit accesses by making Wn along with
En a common input to any combination of the discrete memory
die.
W3
E3
W2
E2
W1
E1
W0
E0
A(18:0)
G
512K x 8
512K x 8
512K x 8
512K x 8
DQ(31:24)
or
DQ3(7:0)
DQ(23:16)
or
DQ2(7:0)
DQ(15:8)
or
DQ1(7:0)
Figure 1. UT8CR512K32 SRAM Block Diagram
DQ(7:0)
or
DQ0(7:0)
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UT8CR512K32-17VCC pdf, ピン配列
WRITE CYCLE
A combination of Wn less than VIL(max) and En less than
VIL(max) defines a write cycle. The state of G is a “don’t care”
for a write cycle. The outputs are placed in the high-impedance
state when either G is greater than VIH(min), or when Wn is less
than VIL(max).
Write Cycle 1, the Write Enable-controlled Access is defined
by a write terminated by Wn going high, with En still active.
The write pulse width is defined by tWLWH when the write is
initiated by Wn, and by tETWH when the write is initiated by En.
Unless the outputs have been previously placed in the high-
impedance state by G, the user must wait tWLQZ before applying
data to the eight bidirectional pins DQn(7:0) to avoid bus
contention.
Write Cycle 2, the Chip Enable-controlled Access is defined by
a write terminated by the former of En or Wn going inactive.
The write pulse width is defined by tWLEF when the write is
initiated by Wn, and by tETEF when the write is initiated by the
En going active. For the Wn initiated write, unless the outputs
have been previously placed in the high-impedance state by G,
the user must wait tWLQZ before applying data to the eight
bidirectional pins DQn (7:0) to avoid bus contention.
RADIATION HARDNESS
The UT8CR512K32 SRAM incorporates special design and
layout features which allows operation in a limited radiation
environment.
Table 2. Radiation Hardness
Design Specifications1
Total Dose
300K
rad(Si)
Heavy Ion
Error Rate2
8.9x10-10 Errors/Bit-Day
Notes:
1. The SRAM is immune to latchup to particles >100MeV-cm2/mg.
2. 10% worst case particle environment, Geosynchronous orbit, 100 mils of
Aluminum.
Supply Sequencing
No supply voltage sequencing is required between VDD1 and
VDD2.
3


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UT8CR512K32-17VCC 電子部品, 半導体
AC CHARACTERISTICS READ CYCLE (Pre and Post-Radiation)*
(-55°C to +125°C for (C) screening and -40°C to +125°C for (W) screening, VDD1 = VDD1 (min), VDD2 = VDD2 (min))
SYMBOL
PARAMETER
8CR512-155
UNIT
tAVAV1
tAVQV
tAXQX2
tGLQX1,2
tGLQV
tGHQZ2
tETQX2,3
tETQV3
tEFQZ4
Read cycle time
Read access time
Output hold time
G-controlled output enable time
G-controlled output enable time
G-controlled output three-state time
E-controlled output enable time
E-controlled access time
E-controlled output three-state time2
MIN
17
MAX
17
3
0
7
7
5
17
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Guaranteed, but not tested.
2. Three-state is defined as a 200mV change from steady-state output voltage.
3. The ET (enable true) notation refers to the latter falling edge of EN. SEU immunity does not affect the read parameters.
4. The EF (enable false) notation refers to the latter rising edge of EN. SEU immunity does not affect the read parameters.
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