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UT62L1024SC-35LL の電気的特性と機能

UT62L1024SC-35LLのメーカーはETCです、この部品の機能は「128K X 8 BIT LOW POWER CMOS SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 UT62L1024SC-35LL
部品説明 128K X 8 BIT LOW POWER CMOS SRAM
メーカ ETC
ロゴ ETC ロゴ 




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UT62L1024SC-35LL Datasheet, UT62L1024SC-35LL PDF,ピン配置, 機能
UTRON
Rev. 1.7
UT62L1024
128K X 8 BIT LOW POWER CMOS SRAM
FEATURES
„ Access time : 35/55/70ns (max.)
„ Low power consumption :
Operating : 40/35/30 mA (typical)
Standby : 2.5µA (typical) L-version
0.5µA (typical) LL-version
„ Power supply range : 2.7V to 3.6V
„ All inputs and outputs TTL compatible
„ Fully static operation
„ Three state outputs
„ Data retention voltage : 2V (min.)
„ Package : 32-pin 600 mil PDIP
32-pin 450 mil SOP
32-pin 8x20 mm TSOP-1
32-pin 8x13.4 mm STSOP
GENERAL DESCRIPTION
The UT62L1024 is a 1,048,576-bit low power
CMOS static random access memory organized
as 131,072 words by 8 bits. It is fabricated using
high performance, high reliability CMOS
technology.
Easy memory expansion is provided by using
two chip enable input.( CE 1 ,CE2) It is
particularly well suited for battery back-up
nonvolatile memory application.
The UT62L1024 operates from a single 2.7V~
3.6V power supply and all inputs and outputs
are fully TTL compatible.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
Vcc
Vss
DECODER
2048 × 512
MEMORY
ARRAY
I/O1-I/O8
I/O DATA
CIRCUIT
COLUMN I/O
CE1
CE2
OE
WE
CONTROL
CIRCUIT
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
P80033

1 Page





UT62L1024SC-35LL pdf, ピン配列
UTRON
Rev. 1.7
UT62L1024
128K X 8 BIT LOW POWER CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
SYMBOL
RATING
UNIT
Terminal Voltage with Respect to Vss
Operating Temperature
VTERM
TA
-0.5 to +4.6
0 to +70
V
Storage Temperature
TSTG
-65 to +150
Power Dissipation
DC Output Current
Soldering Temperature (under 10 sec)
PD
IOUT
Tsolder
1
50
260
W
mA
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect
device reliability.
TRUTH TABLE
MODE
CE1 CE2 OE WE I/O OPERATION
Standby
H
XXX
High - Z
Standby
X
L XX
High -Z
Output Disable
L
HHH
High - Z
Read
L HL H
Write
L HXL
Note: H = VIH, L=VIL, X = Don't care.
DOUT
DIN
SUPPLY CURRENT
ISB,ISB1
ISB,ISB1
ICC , ICC1
ICC , ICC1
ICC , ICC1
DC ELECTRICAL CHARACTERISTICS (VCC = 2.7V~3.6V, Ta = 0to +70)
PARAMETER
SYMBOL TEST CONDITION
Input High Voltage
VIH
Input Low Voltage
VIL
Input Leakage Current IIL
VSS VIN VCC
Output Leakage Current IOL
VSS VI/OVCC
CE 1 =VIH or CE2 = VIL or
MIN.
2.0
- 0.5
-1
TYP. MAX. UNIT
- VCC+0.5 V
- 0.6 V
- 1 µA
-1 -
1 µA
Output High Voltage
Output Low Voltage
Average Operating
Power Supply Courrent
VOH
VOL
ICC
OE = VIH or WE = VIL
IOH = - 1mA
2.2
IOL= 4mA
-
Cycle time =Min. 100% Duty, 35 -
CE 1 =VIL, CE2 = VIH,
II/O = 0mA
55 -
70 -
-
-
40
35
30
-V
0.4 V
60 mA
50 mA
40 mA
Standby Power
Supply Current
ICC1 Cycle time = 1µs, 100% Duty,
. CE 1 0.2V,CE2VCC-0.2V,
--
5 mA
II/O = 0mA
ISB CE 1 =VIH or CE2 = VIL
- - 1.0 mA
ISB1 CE 1 VCC-0.2V or
.CE20.2V
-L -
2.5
100
20*
µA
-
LL
-
0.5
40
10*
µA
*Those parameters are for reference only under 50
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
P80033


3Pages


UT62L1024SC-35LL 電子部品, 半導体
UTRON
Rev. 1.7
UT62L1024
128K X 8 BIT LOW POWER CMOS SRAM
WRITE CYCLE 1 ( WE Controlled) (1,2,3,5)
Address
t WC
CE1
CE2
WE
t AS
t AW
t CW1
t CW2
t WP
t WR
Dout
Din
t WHZ
(4)
High-Z
t DW
t OW
t DH
Data Valid
WRITE CYCLE 2 ( CE 1 and CE2 Controlled) (1,2,5)
t WC
Address
CE1
CE2
t AS
t AW
t CW1
t CW2
t WR
(4)
WE
Dout
Din
t WHZ
t WP
High-Z
t DW
t DH
Data Valid
Notes :
1. WE or CE 1 must be HIGH or CE2 must be LOW during all address transitions.
2. A write occurs during the overlap of a low CE 1 , a high CE2 and a low WE .
3. During a WE controlled with write cycle with OE LOW, tWP must be greater than tWHZ+tDW to allow the I/O drivers to turn
off and data to be placed on the bus.
4. During this period, I/O pins are in the output state, and input singals must not be applied.
4. If the CE 1 LOW transition occurs simultaneously with or after WE LOW transition, the outputs remain in a high Impedance
state.
6. tOW and tWHZ are specified with CL=5pF. Transition is measured ± 500mV from steady state.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
6
P80033

6 Page



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部品番号部品説明メーカ
UT62L1024SC-35L

128K X 8 BIT LOW POWER CMOS SRAM

ETC
ETC
UT62L1024SC-35LL

128K X 8 BIT LOW POWER CMOS SRAM

ETC
ETC


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