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UT6264CSC-70のメーカーはETCです、この部品の機能は「8K X 8 BIT LOW POWER CMOS SRAM」です。 |
部品番号 | UT6264CSC-70 |
| |
部品説明 | 8K X 8 BIT LOW POWER CMOS SRAM | ||
メーカ | ETC | ||
ロゴ | |||
このページの下部にプレビューとUT6264CSC-70ダウンロード(pdfファイル)リンクがあります。 Total 10 pages
UTRON
Rev. 1.1
FEATURES
Access time : 35/70ns (max.)
Low power consumption :
Operating : 45/30 mA (typ.)
CMOS Standby : 2mA (typ.) normal
2 µA (typ.) L-version
1 µA (typ.) LL-version
Single 4.5V~5.5V power supply
Operating temperature :
Commercial : 0℃~70℃
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 28-pin 600 mil PDIP
28-pin 330 mil SOP
FUNCTIONAL BLOCK DIAGRAM
A0-A12
Vcc
Vss
DECODER
8K × 8
MEMORY
ARRAY
I/O1-I/O8
I/O DATA
CIRCUIT
COLUMN I/O
CE1
CE2
OE
WE
CONTROL
CIRCUIT
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
The UT6264C is a 65,536-bit low power CMOS
static random access memory organized as 8,192
words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.
Easy memory expansion is provided by using two
chip enable input.( CE 1 ,CE2) ,and supports low
data retention voltage for battery back-up
operation with low data retention current.
The UT6264C operates from a single 4.5V~5.5V
power supply and all inputs and outputs are fully
TTL compatible.
PIN CONFIGURATION
NC 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
I/O1 11
I/O2 12
I/O3 13
Vss 14
28 Vcc
27 WE
26 CE2
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE1
19 I/O8
18 I/O7
17 I/O6
16 I/O5
15 I/O4
PDIP/SOP
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0 - A12
Address Inputs
I/O1 - I/O8
Data Inputs/Outputs
CE1 ,CE2
Chip Enable Inputs
WE Write Enable Input
OE Output Enable Input
VCC Power Supply
VSS Ground
NC No connection
GENERAL DESCRIPTION
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
P80028
1 Page
UTRON
Rev. 1.1
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
CAPACITANCE (TA=25℃, f=1.0MHz)
PARAMETER
SYMBOL
MIN.
Input Capacitance
CIN -
Input/Output Capacitance
CI/O
-
Note : These parameters are guaranteed by device characterization, but not production tested.
MAX
8
10
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
5ns
1.5V
CL = 100pF, IOH/IOL = -1mA/4mA
UNIT
pF
pF
AC ELECTRICAL CHARACTERISTICS (VCC = 4.5V~5.5V, TA = 0℃ to 70℃)
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
SYMBOL
tRC
tAA
tACE1, tACE2
tOE
tCLZ1*, tCLZ2*
tOLZ*
tCHZ1*, tCHZ2*
tOHZ*
tOH
UT6264C-35
MIN.
MAX.
35 -
- 35
- 35
- 25
10 -
5-
- 25
- 25
5-
UT6264C-70
MIN.
MAX.
70 -
- 70
- 70
- 35
10 -
5-
- 35
- 35
5-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2) WRITE CYCLE
PARAMETER
SYMBOL
UT6264C-35
MIN.
MAX.
Write Cycle Time
tWC 35 -
Address Valid to End of Write
tAW
30 -
Chip Enable to End of Write
tCW1, tCW2 30 -
Address Set-up Time
tAS 0 -
Write Pulse Width
tWP 25 -
Write Recovery Time
tWR 0 -
Data to Write Time Overlap
tDW
20 -
Data Hold from End of Write-Time
tDH
0-
Output Active from End of Write
tOW*
5-
Write to Output in High-Z
tWHZ*
- 15
*These parameters are guaranteed by device characterization, but not production tested.
UT6264C-70
MIN.
MAX.
70 -
60 -
60 -
0-
50 -
0-
30 -
0-
5-
- 25
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
P80028
3Pages
UTRON
Rev. 1.1
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
DATA RETENTION CHARACTERISTICS (TA = 0℃ to 70℃)
PARAMETER
Vcc for Data Retention
Data Retention Current
Chip Disable to Data
Retention Time
Recovery Time
tRC* = Read Cycle Time
SYMBOL
TEST CONDITION
VDR CE1 ≧ VCC-0.2V or CE2 ≤ 0.2V
Vcc=2V
-L
IDR CE1≧VCC-0.2V or CE2 ≤ 0.2V -LL
tCDR
See Data RetentionWaveforms
(below)
tR
DATA RETENTION WAVEFORM
MIN.
2.0
-
-
TYP.
-
1
0.5
MAX. UNIT
5.5 V
50 µA
20 µA
0 - - ns
tRC* -
- ns
Low Vcc Data Retention Waveform (1) ( CE 1 controlled)
Data Retention Mode
VCC
Vcc
VDR ≧ 2V
tCDR
CE1
VIH
CE1 ≧ VCC-0.2V
Vcc
tR
VIH
Low Vcc Data Retention Waveform (2) (CE2 controlled)
Data Retention Mode
VCC
Vcc
VDR ≧ 2V
CE2
tCDR
VIL
CE2 ≦ 0.2V
Vcc
tR
VIL
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
6
P80028
6 Page | |||
ページ | 合計 : 10 ページ | ||
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PDF ダウンロード | [ UT6264CSC-70 データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
UT6264CSC-70 | 8K X 8 BIT LOW POWER CMOS SRAM | ETC |
UT6264CSC-70L | 8K X 8 BIT LOW POWER CMOS SRAM | ETC |
UT6264CSC-70LL | 8K X 8 BIT LOW POWER CMOS SRAM | ETC |