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UT62256CSC-35 の電気的特性と機能

UT62256CSC-35のメーカーはETCです、この部品の機能は「32K X 8 BIT LOW POWER CMOS SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 UT62256CSC-35
部品説明 32K X 8 BIT LOW POWER CMOS SRAM
メーカ ETC
ロゴ ETC ロゴ 




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UT62256CSC-35 Datasheet, UT62256CSC-35 PDF,ピン配置, 機能
Rev. 1.0
UTRON
UT62256C
32K X 8 BIT LOW POWER CMOS SRAM
FEATURES
GENERAL DESCRIPTION
Access time : 35/70ns (max.)
Low power consumption:
Operating : 40/30 mA (typical.)
Standby : 3mA (typical) normal
2uA (typical) L-version
1uA (typical) LL-version
Single 5V power supply
All inputs and outputs are TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 28-pin 600 mil PDIP
28-pin 330 mil SOP
28-pin 8mmx13.4mm STSOP
The UT62256C is a 262,144-bit low power
CMOS static random access memory
organized as 32,768 words by 8 bits. It is
fabricated using high performance, high
reliability CMOS technology.
The UT62256C is designed for high-speed
and low power application. It is particularly
well suited for battery back-up nonvolatile
memory application.
The UT62256C operates from a single 5V
power supply and all inputs and outputs are
fully TTL compatible
FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION
A4
A3
A14 .
.A13 ROW
A12 DECODER
A7
A6 .
A5
A8
I/O1
...
... I/O
CONTROL
I/O8
...
MEMORYARRAY
512 ROWS × 512 COLUMNS
. ..
COLUMNI/O
COLUMNDECODER
VCC
VSS
CE LOGIC
WE CONTROL
OE
A10 A9 A11 A2 A1 A0
PIN DESCRIPTION
SYMBOL
A0 - A14
I/O1 - I/O8
CE
WE
OE
VCC
VSS
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Power Supply
Ground
OE
A11
A9
A8
A13
WE
Vcc
A14
A12
A7
A6
A5
A4
A3
A14 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
I/O1 11
I/O2 12
I/O3 13
Vss 14
28 Vcc
27 WE
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 I/O8
18 I/O7
17 I/O6
16 I/O5
15 I/O4
PDIP/SOP
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 UT62256C 21
9 20
10 19
11 18
12 17
13 16
14 15
STSOP
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
____________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80027
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1

1 Page





UT62256CSC-35 pdf, ピン配列
Rev. 1.0
UTRON
UT62256C
32K X 8 BIT LOW POWER CMOS SRAM
CAPACITANCE (TA=25, f=1.0MHz)
PARAMETER
SYMBOL
MIN.
MAX
Input Capacitance
CIN -
8
Input/Output Capacitance
CI/O
-
10
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
UNIT
pF
pF
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
5ns
1.5V
CL = 100pF, IOH/IOL = -1mA/4mA
AC ELECTRICAL CHARACTERISTICS (VCC = 5V±10% , TA = 0to 70)
(1) READ CYCLE
PARAMETER
SYMBOL
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
tRC
tAA
tACE
tOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
UT62256C-35
MIN. MAX.
35 -
- 35
- 35
- 25
10 -
5-
- 25
- 25
5-
UT62256C-70
MIN. MAX.
70 -
- 70
- 70
- 35
10 -
5-
- 35
- 35
5-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2) WRITE CYCLE
PARAMETER
SYMBOL UT62256C-35 UT62256C-70
MIN. MAX. MIN. MAX.
Write Cycle Time
tWC 35 - 70
Address Valid to End of Write
tAW 30 - 60
Chip Enable to End of Write
tCW 30 - 60
Address Set-up Time
tAS 0 - 0
Write Pulse Width
tWP 25 - 50
Write Recovery Time
tWR 0 - 0
Data to Write Time Overlap
tDW 20 - 30
Data Hold from End of Write Time
tDH
0-0
Output Active from End of Write
tOW*
5-5
Write to Output in High Z
tWHZ*
- 15 -
*These parameters are guaranteed by device characterization, but not production tested.
-
-
-
-
-
-
-
-
-
25
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
_____________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80027
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3


3Pages


UT62256CSC-35 電子部品, 半導体
Rev. 1.0
UTRON
UT62256C
32K X 8 BIT LOW POWER CMOS SRAM
DATA RETENTION CHARACTERISTICS (TA = 0to 70)
PARAMETER
Vcc for Data Retention
Data Retention Current
Chip Disable to Data
Retention Time
Recovery Time
tRC* = Read Cycle Time
SYMBOL TEST CONDITION
VDR CE VCC-0.2V
IDR Vcc=3V
CE VCC-0.2V
tCDR See Data Retention
Waveforms (below)
tR
DATA RETENTION WAVEFORM
VCC
CE
4.5V
tCDR
Data Retention Mode
VDR 2V
MIN. TYP. MAX. UNIT
2.0 - 5.5 V
-L -
- LL -
0
1 50 µA
0.5 20 µA
- - ns
tRC* -
- ns
4.5V
tR
VSS
CE VCC -0.2V
_____________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80027
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
6

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
UT62256CSC-35

32K X 8 BIT LOW POWER CMOS SRAM

ETC
ETC
UT62256CSC-35L

32K X 8 BIT LOW POWER CMOS SRAM

ETC
ETC
UT62256CSC-35LL

32K X 8 BIT LOW POWER CMOS SRAM

ETC
ETC


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