DataSheet.jp

UT621024LS-70LL の電気的特性と機能

UT621024LS-70LLのメーカーはETCです、この部品の機能は「128K X 8 BIT LOW POWER CMOS SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 UT621024LS-70LL
部品説明 128K X 8 BIT LOW POWER CMOS SRAM
メーカ ETC
ロゴ ETC ロゴ 




このページの下部にプレビューとUT621024LS-70LLダウンロード(pdfファイル)リンクがあります。
Total 12 pages

No Preview Available !

UT621024LS-70LL Datasheet, UT621024LS-70LL PDF,ピン配置, 機能
UTRON
UT621024
Rev. 1.5
128K X 8 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
FEATURES
The UT621024 is a 1,048,576-bit low power
„ Access time : 35/55/70ns (max.)
„ Low power consumption :
Operating : 60/50/40 mA (typical)
Standby : 2µA (typical) L-version
CMOS static random access memory
organized as 131,072 words by 8 bits. It is
fabricated using high performance, high
reliability CMOS technology.
1µA (typical) LL-version
„ Single 5V power supply
„ All inputs and outputs TTL compatible
„ Fully static operation
„ Three state outputs
The UT621024 is designed for low power
application. It is particularly well suited for
battery back-up nonvolatile memory
application.
„ Data retention voltage : 2V (min.)
„ Package : 32-pin 600 mil PDIP
32-pin 450 mil SOP
32-pin 8mmx20mm TSOP-1
The UT621024 operates from a single 5V
power supply and all inputs and outputs are
fully TTL compatible.
32-pin 8mmx13.4mm STSOP
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
A16
A15
A13 .
A14
.A12
A7 ROW
DECODER
A6 .
A5
A4
A8
I/O1
...
... I/O
CONTROL
I/O8
...
MEMORY ARRAY
1024 ROWS× 1024 COLUMNS
. ..
COLUMN I/O
COLUMN DECODER
VCC
VSS
NC 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O1 13
I/O2 14
I/O3 15
Vss 16
32 Vcc
31 A15
30 CE2
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE1
21 I/O8
20 I/O7
19 I/O6
18 I/O5
17 I/O4
PDIP / SOP
CE1
CE2
WE
OE
LOGIC
CONTROL
A10 A11 A9 A3 A2 A1 A0
PIN DESCRIPTION
SYMBOL
A0 - A16
I/O1 - I/O8
CE1 ,CE2
WE
OE
VCC
VSS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip enable 1,2 Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
A11
A9
A8
A13
WE
CE2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
UT621024
TSOP-I/STSOP
32 OE
31 A10
30 CE1
29 I/O8
28 I/O7
27 I/O6
26 I/O5
25 I/O4
24 Vss
23 I/O3
22 I/O2
21 I/O1
20 A0
19 A1
18 A2
17 A3
________________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1

1 Page





UT621024LS-70LL pdf, ピン配列
UTRON
Rev. 1.5
UT621024
128K X 8 BIT LOW POWER CMOS SRAM
CAPACITANCE (TA=25, f=1.0MHz)
PARAMETER
SYMBOL
MIN.
MAX.
Input Capacitance
CIN - 8
Input/Output Capacitance
CI/O - 10
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
UNIT
pF
pF
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
5ns
1.5V
CL=100pF, IOH/IOL=-1mA/4mA
AC ELECTRICAL CHARACTERISTICS (VCC = 5V± 10% , TA = 0to 70)
(1) READ CYCLE
PARAMETER
SYMBOL UT621024-35 UT621024-55 UT621024-70 UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time
tRC 35 - 55 - 70 - ns
Address Access Time
tAA - 35 - 55 - 70 ns
Chip Enable Access Time
tACE1, tACE2
-
35
-
55
-
70 ns
Output Enable Access Time
tOE
- 25 - 30 - 35 ns
Chip Enable to Output in Low-Z tCLZ1*, tCLZ2* 10 - 10 - 10 - ns
Output Enable to Output in Low-Z tOLZ*
5 - 5 - 5 - ns
Chip Disable to Output in High-Z tCHZ1*, tCHZ2* - 25 - 30 - 35 ns
Output Disable to Output in High-Z tOHZ*
- 25 - 30 - 35 ns
Output Hold from Address Change tOH
5 - 5 - 5 - ns
(2) WRITE CYCLE
PARAMETER
SYMBOL UT621024-
35
UT621024-55 UT621024-70
MIN. MAX. MIN. MAX. MIN. MAX.
Write Cycle Time
tWC 35 - 55 - 70 -
Address Valid to End of Write
tAW
30 - 50 - 60 -
Chip Enable to End of Write
tCW1, tCW2
30
-
50
-
60
-
Address Set-up Time
tAS 0 - 0 - 0 -
Write Pulse Width
tWP 25 - 40 - 45 -
Write Recovery Time
tWR 0 - 0 - 0 -
Data to Write Time Overlap
tDW
20 - 25 - 30 -
Data Hold from End of Write-Time tDH
0-0-0-
Output Active from End of Write tOW*
5-5-5-
Write to Output in High-Z
tWHZ*
- 15 - 20 - 25
*These parameters are guaranteed by device characterization, but not production tested.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3


3Pages


UT621024LS-70LL 電子部品, 半導体
UTRON
Rev. 1.5
UT621024
128K X 8 BIT LOW POWER CMOS SRAM
DATA RETENTION CHARACTERISTICS (TA = 0to 70)
PARAMETER
Vcc for Data Retention
Data Retention Current
SYMBOL TEST CONDITION
VDR CE1 VCC-0.2V or
CE2 0.2V
IDR Vcc=3V
CE1 VCC-0.2V or
CE2 0.2V
Chip Disable to Data
Retention Time
tCDR See Data Retention
Waveforms (below)
Recovery Time
tR
tRC* = Read Cycle Time
*Those parameters are for reference only under 50
MIN. TYP. MAX. UNIT
2.0 -
-
V
-L
-
1
40 µA
20*
- LL
-
0.5
20
10*
µA
0 - - ns
tRC* - - ns
DATA RETENTION WAVEFORM
VCC
CE1
VSS
CE2
4.5V
tCDR
VIH
VIL
Date Retention Mode
VDR 2.0V
CE1 VCC -0.2V
CE2 0.2V
4.5V
tR
VIH
VIL
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
6

6 Page



ページ 合計 : 12 ページ
 
PDF
ダウンロード
[ UT621024LS-70LL データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
UT621024LS-70L

128K X 8 BIT LOW POWER CMOS SRAM

ETC
ETC
UT621024LS-70LL

128K X 8 BIT LOW POWER CMOS SRAM

ETC
ETC


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap