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PDF USB1T1102 Data sheet ( Hoja de datos )
| Número de pieza | USB1T1102 | |
| Descripción | Universal Serial Bus Peripheral Transceiver with Voltage Regulator | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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August 2004
Revised August 2004
USB1T1102 • USB1T1102R (Preliminary)
Universal Serial Bus Peripheral Transceiver
with Voltage Regulator
General Description
This chip provides a USB Transceiver functionality with a
voltage regulator that is compliant to USB Specification
Rev 2.0. this integrated 5V to 3.3V regulator allows inter-
facing of USB Application specific devices with supply volt-
ages ranging from 1.65V to 3.6V with the physical layer of
Universal Serial Bus. It is capable of operating at 12Mbits/s
(full speed) data rates and hence is fully compliant to USB
Specification Rev 2.0. The Vbusmon pin allows for monitor-
ing the Vbus line.
The USB1T1102 also provides exceptional ESD protection
with 15kV contact HBM on D+, D− pins.
Features
s Complies with Universal Serial Bus Specification 2.0
s Integrated 5V to 3.3V voltage regulator for powering
VBus
s Utilizes digital inputs and outputs to transmit and receive
USB cable data
s Supports full speed (12Mbits/s) data rates
s Ideal for portable electronic devices
s MLP technology package (16 pin) with HBCC footprint
s 15kV contact HBM ESD protection on bus pins
Ordering Code:
Order Number Package Number
Package Description
USB1T1102MPX
MLP14D
14-Terminal Molded Leadless Package (MLP), 2.5mm Square
USB1T1102RMPX
(Preliminary)
MLP14D
14-Terminal Molded Leadless Package (MLP), 2.5mm Square
USB1T1102MHX
MLP16HB
16-Terminal Molded Leadless Package (MHBCC), JEDEC MO-217, 3mm Square
USB1T1102RMHX
(Preliminary)
MLP16HB
16-Terminal Molded Leadless Package (MHBCC), JEDEC MO-217, 3mm Square
Logic Diagram
Note: On the USB1T1102R the 1.5k resistor is integrated into the part, and connects VPU and D+ eliminating the need for this external pull-up resistor.
© 2004 Fairchild Semiconductor Corporation DS500877
www.fairchildsemi.com
1 page  
ESD Protection
ESD Performance of the USB1T1102
HBM D+/D−: 15.0kV
HBM, all other pins (Mil-Std 883E): 6.5kV
ESD Protection: D+/D− Pins
Since the differential pins of a USB transceiver may be
subjected to extreme ESD voltages, additional immunity
has been included in the D+ and D− pins without compro-
mising performance. The USB1T1102 differential pins have
ESD protection to the following limits:
• 15kV using the contact Human Body Model
• 8kV using the Contact Discharge method as specified in
IEC 61000-4-2
Human Body Model
Figure 1 shows the schematic representation of the Human
Body Model ESD event. Figure 2 is the ideal waveform rep-
resentation of the Human Body Model.
IEC 61000-4-2, IEC 60749-26 and IEC 60749-27
The IEC 61000-4-2 standard covers ESD testing and per-
formance of finished equipment, and as such evaluates the
equipment in its entirety for ESD immunity. Fairchild
Semiconductor has evaluated this device using the
IEC 6100-4-2 representative system model depicted in Fig-
ure 3. Under the additional standards set forth by the IEC,
this device is also compliant with IEC 60749-26 (HBM) and
IEC 60749-27 (MM).
Additional ESD Test Conditions
For additional information regarding our product test meth-
odologies and performance levels, please contact Fairchild
Semiconductor.
FIGURE 1. Human Body ESD Test Model
FIGURE 2. HBM Current Waveform
FIGURE 3. IEC 61000-4-2 ESD Test Model
5 www.fairchildsemi.com
5 Page 
AC Waveforms
FIGURE 4. Rise and Fall Times
FIGURE 5. Vpo, Vmo to D+/D−
FIGURE 6. D+/D− to RCV, Vpo/Vp and Vmo/Vm
Test Circuits and Waveforms
FIGURE 7. OE to D+/D−
CL = 50 pF Full Speed Propagation Delays
CL = −125 pF Edge Rates only
FIGURE 8. Load for D+/D−
V = 0 for tPZH, tPHZ
V = VREG for tPZL
FIGURE 9. Load for Enable and Disable Times
FIGURE 10. Load for Vm/Vmo, Vp/Vpo and RCV
11 www.fairchildsemi.com
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet USB1T1102.PDF ] | |
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