DataSheet.jp

UPD98411GN-MMU の電気的特性と機能

UPD98411GN-MMUのメーカーはNECです、この部品の機能は「ATM QUAD SONET FRAMER」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD98411GN-MMU
部品説明 ATM QUAD SONET FRAMER
メーカ NEC
ロゴ NEC ロゴ 




このページの下部にプレビューとUPD98411GN-MMUダウンロード(pdfファイル)リンクがあります。

Total 30 pages

No Preview Available !

UPD98411GN-MMU Datasheet, UPD98411GN-MMU PDF,ピン配置, 機能
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD98411
ATM QUAD SONET FRAMER
The µPD98411 NEASCOT-P40 is one of ATM-LAN LSIs and provides the functions of the TC sublayer of the
SONET/SDH-base physical layer of the ATM protocol specified by the ATM Forum. Its main functions include a
transmission function to map an ATM cell passed from an ATM layer to the payload of 155M-bps SONET STS-
3c/SDH STM-1 frame and transmit the cell to the PMD (Physical Media Dependent) sublayer of the physical layer,
and a reception function to separate the overhead and ATM cell from the data string received from the PMD device
and transmit the ATM cell to the ATM layer. The µPD98411 NEASCOT-P40 combines these transmission
/reception functions into a port function that is realized as a single 4-port LSI chip. This LSI is ideally suited for
use in the ATM hubs, ATM switches, and other equipment used to configure an ATM network.
In addition, the µPD98411 also has a clock recovery function for each port to extract synchronous clock for
reception of receive data from the bit stream, and a clock synthesis function to generate a clock for transmission.
For the details of functional description, refer to the following user's manual.
µPD98411 User's Manual : S12736E
FEATURES
Incorporates an ATM user network interface TC sublayer function for four channels.
Conforms to ATM FORUM UNI v3.1.
Incorporates four clock recovery PLLs and one clock synthesizer PLL.
Conforms to ATM FORUM UTOPIA Level 2 v1.0.
ATM layers can be selected from the multi-PHY interface (up to 800 Mbps) in several different modes.
Single 16-bit
Single 8-bit
Dual 8-bit
1TCLAV/1RCLAV (Cell Available signal mode)
Direct Status Indication mode
Multiplexed Status Polling mode
A management interface can be set to either of two modes.
RD-WR-RDY style (Intel-compatible mode)
DS-R/W-ACK style (Motorola-compatible mode)
The line-side PMD interface accepts a P-ECL level input.
Supports a loopback function.
Supports a pseudo error generation frame transmission function.
Incorporates one general input port per channel and three output ports (each able to drive an LED) per
channel.
Supports JTAG boundary scan test (IEEE 1149.1).
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S12953EJ4V0DS00 (4th edition)
Date Published January 1999 NS CP(K)
Printed in Japan
©NEC Corporation 1997,1999

1 Page





UPD98411GN-MMU pdf, ピン配列
APPLICATIONS
The following are examples of the application using the µPD98411.
ATM Switches
µPD98411
NIC
155 ATM Interface
NIC
NIC
µPD98411
µPD98411
µPD98411
OC-12
SONET Framer
SWITCH
µPD98411
UTOPIA Level2
CPU
Backbone
Network
Data Sheet S12953EJ4V0DS00
3


3Pages


UPD98411GN-MMU 電子部品, 半導体
155.52 MHz
PECL serial interface
Conforms to UTOPIA level 2 multi-PHY
interface of 400 to 800 Mbps
Clock
Recovery
S/P
Port0
P/S
Rx framer block
Rx timing generation Descramble
BIP generation Overhead extraction
Tx framer block
Tx timing generation Scramble
BIP generation Overhead setup
Rx ATM cell processor block
HEC compare/control Cell descramble
Cell synchronization Idle cell drop
Tx ATM cell processor block
HEC generation Cell scramble
Cell mapping Idle cell insertion
RX FIFO
(8 cells)
TX FIFO
(8 cells)
Clock
S/P
Recovery
Rx framer block
Rx ATM cell processor block
RX FIFO
CloPc/kS
recovery
S/PTX FramerRxBfrlaomcker block
Tx ATM CellRsxOApTeMratceeBlllopcrokcessor block
Tx FIFO
6 Cells
RX FIFO
Port1
CloPc/kS
recovery
S/PTX FramerRxBfrlaomcker block
Tx ATM CellRsxOApTerMateceBlllopcrokcessor block
Tx FIFO
6 Cells
RX FIFO
Port2
P/S Tx framer block
Tx ATM cell processor block
TX FIFO
Port3
Clock
Synthesizer
JTAG
OAM sequencer
Mode
registers
Test
registers
Performance
registers
Interrupt cause Tx/Rx overhead
registers
registers
Management
interface
CPU Bus Interface
Address: 9 bits
Data: 8 bits

6 Page



ページ 合計 : 30 ページ
 
PDF
ダウンロード
[ UPD98411GN-MMU データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
UPD98411GN-MMU

ATM QUAD SONET FRAMER

NEC
NEC


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap