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PDF UPD98402AGM-KED Data sheet ( Hoja de datos )
| Número de pieza | UPD98402AGM-KED | |
| Descripción | LOCAL ATM SONET FRAMER | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD98402A
LOCAL ATM SONET FRAMER
The µPD98402A is one of the ATM-LAN LSIs and incorporates the TC sublayer function in the SONET/SDH-
based physical layer of the ATM protocol. The main functions of the µPD98402A include a transmit function for
mapping ATM cells received from the ATM layer onto the payload block of the SONET STS-3c/SDH STM-1 frame
and sending them to PMD (Physical Media Dependent) in the physical layer, and a receive function for separating
the overhead block and ATM cells from the data string received from the PMD sublayer and sending the ATM cells
to the ATM layer.
Futhermore, the µPD98402A is compliant with the ATM Forum UNI Recommendations.
FEATURES
• Provision of TC sublayer function of ATM protocol physical layer
• Support of SONET STS-3c frame/SDH STM-1 frame format
• Provision of stop mode for cell scramble/descramble and frame scramble/descramble
• Disposal/transitory selection of unassigned cells is possible.
• Compliant with UTOPIA interface
• Incorporation of internal loopback function at PMD and ATM layer turns
• PMD interface
155.52 Mbps serial interface
19.44 MHz parallel interface
• Provided with registers for writing/reading overhead information
SOH (section overhead): C1 (1st to 3rd) bytes, F1 byte
LOH (line overhead): K2 byte
POH (pass overhead): F2 byte, C2 byte
• CMOS process
• +5 V single power supply
The information in this document is subject to change without notice.
Document No. S10835EJ1V0DS00 (1st edition)
Date Published December 1995 P
Printed in Japan
©
1995
1 page  
FUNCTIONAL PIN GROUPS
Control
PMD
Interface
OAM
Interface
RDIC
RDIT
RCIC
RCIT
TDOC
TDOT
TCOC
TCOT
TFKC
TFKT
TPD0-TPD7
8
TPC
TFC
RPD0-RPD7
8
RPC
PSEL
RAL
TAL
LOS
OOF
µPD98402A
RDO0-RDO7
RCLK
RSOC
RENBL
EMPTY
TDI0-TDI7
TCLK
TSOC
TENBL
FULL
8
8
D0-D7
A0-A5
R/W
CE
ACK
PHINT
OE
8
6
ATM Layer
Interface
Management
Interface
JTAG boundary scanNote pin
Note This function can be supported at the customer’s request.
5
5 Page 
µPD98402A
• Control
Symbol
TFSS
RESET
TCL
RCL
TxFP
RxFP
Pin No.
29
I/O
I
103 I
32 O
85 O
31 O
30 O
I/O Level
TTL
TTL
CMOS
CMOS
CMOS
CMOS
Function
This is the transmit frame setting signal input pin.
It allows synchronization timing of transmit frame output to be
set. The µPD98402A samples this input signal by the internal
transmit system clock (TCL).
Initial output of the transmit frame is restarted 9 clocks into
TCL clock cycle after a high level is latched at TCL rise.
This is the system reset signal input pin.
It initializes the µPD98402A. It is necessary to input a reset
signal with a pulse width of 2 cycles or more of the clock that
has the longest cycle among the following clocks input to the
µPD98402A.
ATM layer : TCLK, RCLK clock cycles
PMD layer : 1/8 cycle of TFKT/TFKC, RCIC/RCIT clocks,
TFC, RPC clock cycles
Immediately after a reset, no read/write is possible to registers
during 5 clocks of the TCL clock (19.44 MHz).
This pin is used to output an internal transmit system clock.
The µPD98402A outputs as the internal transmit system clock,
the TFKT/TFKC input clock (155.52 MHz) scaled by 8 in serial
interface mode, and the TFC input clock (19.44 MHz) in
parallel interface mode.
This pin is used to output an internal receive system clock.
The µPD98402A outputs as the internal receive system clock,
the RCIC/RCIT input clock (155.52 MHz) scaled by 8 in serial
interface mode, and the RFC input clock (19.44 MHz) in
parallel interface mode.
This is a frame pulse signal on the transmitting side. It
outputs pulses synchronous with the transmit frame start. To
be inactive after reset.
This is a frame pulse signal on the receiving side. It outputs
pulses synchronous with the receive frame start. To be
inactive after reset.
• JTAG boundary scan pins (This function can be supported at the customer’s request.)
Symbol
TJI
TDO
TCK
TMS
TRST
Pin No.
4
3
2
5
6
I/O
I
O
I
I
I
I/O Level
TTL
CMOS
TTL
TTL
TTL
Function
This is a pin for JTAG boundary scan.
Pull it up or ground it in normal operation.
This is a pin for JTAG boundary scan.
Leave it open in normal operation.
This is a pin for JTAG boundary scan.
Pull it up or ground it in normal operation.
This is a pin for JTAG boundary scan.
Pull it up or ground it in normal operation.
This is a pin for JTAG boundary scan.
Ground it in normal operation.
11
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