|
|
PDF UPD98401AGD-MML Data sheet ( Hoja de datos )
| Número de pieza | UPD98401AGD-MML | |
| Descripción | ATM SAR CHIP | |
| Fabricantes | NEC | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de UPD98401AGD-MML (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD98401A
ATM SAR CHIP
DESCRIPTION
The µPD98401A (NEASCOT-S15TM) is a high-performance SAR chip that segments and reassembles ATM cells.
This chip can interface with an ATM network when it is included in a workstation, computer, front-end processor,
network hub, or router. The µPD98401A conforms to the ATM Forum Recommendation, and provides the functions
of the AAL-5 SAR sublayer and ATM layer.
The µPD98401A is compatible with its predecessor, µPD98401, in terms of hardware and software.
Functions are explained in detail in the following User’s Manual. Be sure to read this manual when designing your
system.
µPD98401A User’s Manual: S12054E
FEATURES
• Conforms to ATM Forum
• AAL-5 SAR sublayer and ATM layer functions
• Hardware support of AAL-5 processing
• Processing of non-AAL-5 traffic (AAL-3/4 cell, OAM cell, RM cell) by software with raw cell processing function
• Hardware support of comparison/generation of CRC-10 for non-AAL-5 traffic
• Supports up to 32K virtual channels (VC)
• Provided with 16 traffic shapers that carry out transmission scheduling (control of average rate/peak rate) so as to
set different transmission rate for each VC
• Interface and commands for controlling PHY device
• Employs “UTOPIA interface” as cell data interface with PHY device
- Octet-level handshake
- Cell-level handshake
• 32-bit general-purpose bus interface
• High-speed DMAC (supports 1-, 2-, 4-, 8-, 12-, and 16-word burst)
• JTAG boundary scan test function (IEEE1149.1)
• CMOS technology
• +5 V single power source
Remark In this document, an active low pin is indicated by ×××_B (_B after a pin name).
The information in this document is subject to change without notice.
Document No. S12100EJ3V0DS00 (3rd edition)
Date Published February 1999 N CP(K)
Printed in Japan
The mark shows major revised points.
©
1997
1 page  
µPD98401A
PIN NAMES
ABRT_B
: Abort
AD31_AD0
: Address/Data
ASEL_B
: Slave Address Select
ATTN_B
: Attention/Burst Frame
CA17-CA0
: Control Memory Address
CBE_B3_CBE_B0 : Local Port Byte Enable
CD31-CD0
: Control Memory Data
CLK : Clock
COE_B
: Control Memory Output Enable
CPAR3-CPAR0 : Control Memory Parity
CWE_B
: Control Memory Write Enable
DBMD
: DMA Bus Monitor Data
DBMF
: DMA Bus Monitor First
DBML
: DMA Bus Monitor Last
DBVC
: DMA Bus Monitor VC
DBMR
: DMA Bus Monitor Remaining
DR/W_B
: DMA Read/Write
EMPTY_B/RxCLAV : PHY Output Buffer Empty
ERR_B
: Error
FULL_B/TxCLAV : PHY Buffer Ful
GND
: Ground
GNT_B
: Grant
INITD
: Initialization Disable
INTR_B
: Interrupt
JCK : JTAG Test Pin
JDI : JTAG Test Pin
JDO
: JTAG Test Pin
JMS
: JTAG Test Pin
JRST_B
: JTAG Test Pin
OE_B
: Output Enable
PAR3-PAR0
: Bus Parity
PHCE_B
PHINT_B
PHOE_B
PHRW_B
RCLK
RDY_B
RENBL_B
RSOC
RST_B
Rx7-Rx0
SLE_B
SIZE2-SIZE0
SR/W_B
TCLK
TENBL_B
TSOC
TRF_B
Tx7-Tx0
VDD
: PHY Chip Enable
: PHY Interrupt
: PHY Output Enable
: PHY Read/Write
: Receive Clock
: Target Ready
: Receive Enable
: Receive Start Cell
: Reset
: Receive Data Bus
: Slave Select
: Burst Size
: Slave Read/Write
: Transmit Clock
: Transmit Enable
: Transmit Start of Cell
: Delay Select
: Transmit Data Bus
: Power Supply
Data Sheet S12100EJ3V0DS00
5
5 Page 
µPD98401A
Pin Name
SR/W_B
Pin No.
68
SEL_B
69
ASEL_B
70
CLK
RST_B
32
29
INTR_B
71
I/O I/O Level
Function
(3/3)
I TTL Slave Read/Write.
The SR/W_B signal determines the direction in which the slave is
accessed.
1: Read access
2: Write access
I TTL Slave Select.
This signal goes low (active) when the µPD98401A is accessed as a
slave. The SEL_B signal must goes low as soon as or after the
ASEL_B signal has gone low. An inactive period of at least 2 system
clock cycles must be inserted between when the SEL_B signal has
become inactive and when it becomes active again.
I TTL Slave Address Select.
The ASEL_B signal is used to select the direct address register of the
µPD98401A.
When a low level is input to ASEL_B, the µPD98401A samples the AD
bus at the first rising edge of CLK.
I TTL Clock.
This pin inputs the system clock. Input a clock in a range of 8 to 33
MHz.
I TTL Reset.
The RST_B signal initializes the µPD98401A (on starting, etc.). After
reset, the µPD98401A can start normal operation. When a low level is
input to RST_B, the internal state machine and registers of the
µPD98401A are reset, and all 3-state signals go into a high-
impedance state. The reset input is asynchronous. When this signal
is input during operation, the operating status at that time is lost. Hold
RST_B low at least for the duration of one clock. After reset, do not
access the µPD98401A for at least 20 clock cycles.
O Nch open- Interrupt.
drain output This is an open-drain signal and must be pulled up.
INTR_B informs the CPU that the interrupt bit (unmasked) of the GSR
register is set.
Data Sheet S12100EJ3V0DS00
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet UPD98401AGD-MML.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| UPD98401AGD-MML | ATM SAR CHIP | NEC |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |