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UPD77113A の電気的特性と機能

UPD77113AのメーカーはNECです、この部品の機能は「MOS INTEGRATED CIRCUIT」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD77113A
部品説明 MOS INTEGRATED CIRCUIT
メーカ NEC
ロゴ NEC ロゴ 




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UPD77113A Datasheet, UPD77113A PDF,ピン配置, 機能
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD77113A, 77114
16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSORS
DESCRIPTION
The µPD77113A and 77114 are 16-bit fixed-point digital signal processors (DSPs).
Compared with the µPD77016 family, these DSPs have improved power consumption and are ideal for battery-
powered mobile terminals such as PDAs and cellular phones.
Both mask ROM and RAM models are available.
For details of the functions of these DSPs, refer to the following User’s Manuals:
µPD77111 Family User’s Manual
: U14623E
µPD77016 Family User’s Manual - Instructions : U13116E
FEATURES
z Instruction cycle (operating clock)
µPD77113A : 13.3 ns MIN (75 MHz MAX)
µPD77114 : 13.3 ns MIN (75 MHz MAX)
z Memory
• Internal instruction memory
µPD77113A : RAM 3.5K words × 32 bits
Mask ROM 48K words × 32 bits
µPD77114 : RAM 3.5K words × 32 bits
Mask ROM 48K words × 32 bits
• Data memory
µPD77113A : RAM 16K words × 16 bits × 2 banks
Mask ROM 32K words × 16 bits × 2 banks
µPD77114 : RAM 16K words × 16 bits × 2 banks
Mask ROM 32K words × 16 bits × 2 banks
External memory space 8K words × 16 bits × 2 banks
ORDERING INFORMATION
Part Number
µPD77113AF1-xxx-CN1
µPD77114GC-xxx-9EU
Package
80-pin plastic fine-pitch BGA (9 × 9)
100-pin plastic TQFP (fine pitch) (14 × 14)
Remark xxx indicates ROM code suffix.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14373EJ3V0DS00 (3rd edition)
Date Published February 2001 N CP(K)
Printed in Japan
The mark shows major revised points.
©
1999

1 Page





UPD77113A pdf, ピン配列
µPD77113A, 77114
PIN CONFIGURATION
+2.5 V +3 V
Serial interface #1
Serial interface #2
Port
Host interface
For debugging
SO1
SORQ1
SOEN1
SCK1
SI1
SIEN1
SIAK1
IVDD
SO2
SOEN2
SCK2
SI2
SIEN2
EVDD
RESET
INT1 - INT4
CLKIN
CLKOUT
WAKEUPNote 1
(4) P0 - P3
DA0 - DA12
HCS
X/Y
HA0, HA1
(2) HRD
D0 - D15
MRD
HRE
MWR
HWR
HWE
HD0 - HD7
(8)
HOLDRQ
HOLDAK
BSTB
(2) TDO, TICE
(4)
TCK, TDI, TMS, TRST
GND
Reset, interrupt
(4)
Clock
System control
(13)
External data
(16) memory
Data bus
control
Note 2
Notes 1. The function of this pin can be activated or deactivated by mask option.
2. An external data memory interface is not provided on the µPD77113A.
Data Sheet U14373EJ3V0DS
3


3Pages


UPD77113A 電子部品, 半導体
100-pin plastic TQFP (fine-pitch) (14 × 14) (Top View)
µPD77114GC-xxx-9EU
µPD77113A, 77114
GND
NC
NC
DA12
DA11
DA10
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
D15
D14
D13
D12
D11
D10
D9
D8
EVDD
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1 75
2 74
3 73
4 72
5 71
6 70
7 69
8 68
9 67
10 66
11 65
12 64
13 63
14 62
15 61
16 60
17 59
18 58
19 57
20 56
21 55
22 54
23 53
24 52
25 51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
EVDD
CLKIN
CLKOUT
HA1
HA0
HWR
HRD
HCS
HWE
HRE
GND
EVDD
HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
P0
P1
P2
P3
GND
Note The functions can be activated or deactivated by a mask option.
6 Data Sheet U14373EJ3V0DS

6 Page



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共有リンク

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部品番号部品説明メーカ
UPD77113A

MOS INTEGRATED CIRCUIT

NEC
NEC
UPD77113AF1-XXX-CN1

MOS INTEGRATED CIRCUIT

NEC
NEC


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