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PDF UPD75P3018GK-BE9 Data sheet ( Hoja de datos )
| Número de pieza | UPD75P3018GK-BE9 | |
| Descripción | 4-BIT SINGLE-CHIP MICROCONTROLLER | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75P3018
4-BIT SINGLE-CHIP MICROCONTROLLER
The µPD75P3018 replaces the µPD753017’s internal mask ROM with a one-time PROM, and features expanded ROM
capacity.
Because the µPD75P3018 supports programming by users, it is suitable for use in evaluations of systems in
development stages using the µPD753012, 753016, or 753017, and for use in small-scale production.
The following document describes further details of the functions. Please make sure to read this document
before starting design.
µPD753017 User's Manual : U11282E
FEATURES
Compatible with µPD753017
Memory capacity:
• PROM : 32768 x 8 bits
• RAM : 1024 x 4 bits
Can operate in same power supply voltage as the mask version µPD753017
• VDD = 2.2 to 5.5 V
LCD controller/driver
*
ORDERING INFORMATION
Part Number
µPD75P3018GC-3B9
µPD75P3018GK-BE9
Package
PROM (¥ 8 bits)
80-pin plastic QFP (14 x 14 mm, 0.65-mm pitch)
32768
80-pin plastic TQFP (fine pitch) (12 x 12 mm, 0.5-mm pitch)
32768
Caution Mask-option pull-up resistors are not provided in this device.
The information in this document is subject to change without notice.
Document No. U10956EJ1V0DS00 (1st edition)
(Previous No. IP-3538)
Date Published August 1996 P
Printed in Japan
*The mark shows major revised points.
© 1994
1 page  
2. BLOCK DIAGRAM
µPD75P3018
PTO1/P21
TI1/TI2/
P12/INT2
PTO2/P22/PCL
TIMER/EVENT
COUNTER
#1
INT1
TIMER/EVENT
COUNTER
#2
INT2 TOUT0
TI0/P13
PTO0/P20
BUZ/P23
BASIC
INTERVAL
TIMER/
WATCHDOG
TIMER
INTBT
TIMER/EVENT
COUNTER
#0
INT 0 TOUT0
WATCH
TIMER
INTW fLCD
SI/SB1/P03
SO/SB0/P02
SCK/P01
CLOCKED
SERIAL
INTERFACE
INTCSI TOUT0
INT0/P10
INT1/P11
INT2/P12
INT4/P00
INTERRUPT
CONTROL
KR0/P60 to
KR7/P73
8
BIT SEQ.
BUFFER (16)
PORT0 4 P00 to P03
PROGRAM
COUNTER
(15)
SP (8)
CY
ALU SBS
BANK
PROM
PROGRAM
MEMORY
32768 x 8 BITS
DECODE
AND
CONTROL
GENERAL
REG.
RAM
DATA
MEMORY
1024 x 4 BITS
fx/2 N
CPU CLOCK Φ
CLOCK
OUTPUT
CONTROL
CLOCK
DIVIDER
SYSTEM CLOCK
GENERATOR STAND BY
SUB MAIN CONTROL
PORT1 4 P10 to P13
PORT2 4 P20 to P23
PORT3
4
P30 to P33
/MD0 to MD3
PORT4
4
P40/D0 to
P43/D3
PORT5
4
P50/D4 to
P53/D7
PORT6 4 P60 to P63
PORT7 4 P70 to P73
24 S0 to S23
8
S24/BP0 to
S31/BP7
4
COM0 to
COM3
3 VLC0 to VLC2
fLCD
BIAS
LCDCL/P30
SYNC/P31
PCL/P22
XT1XT2 X1 X2
VDD VSS RESET VPP
5
5 Page 
µPD75P3018
TYPE F-B
Output
disable
(P)
Data
Output
disable
Output
disable
(N)
P.U.R.
enable
*TYPE H-A
VDD
P.U.R.
P-ch
VDD
P-ch
IN/OUT
SEG
data
Type G-A
N-ch
Bit Port
data
Output
disable
Type E-B
IN/OUT
P.U.R. : Pull-Up Resistor
*TYPE G-A
VLC0
VLC1
P-ch
P-ch N-ch
SEG
data
VLC2
N-ch
N-ch
OUT
TYPE M-C
Data
Output
disable
P.U.R.
enable
VDD
P.U.R.
P-ch
IN/OUT
N-ch
P.U.R. : Pull-Up Resistor
TYPE G-B
VLC0
VLC1
P-ch
COM
data
VLC2
N-ch
P-ch N-ch
N-ch P-ch
*TYPE M-E
Data
Output
disable
Input instruction
OUT
VDD
P-ch
N-ch
(+13-V
breakdown
voltage)
P.U.R.Note
IN/OUT
Voltage
controller
(+13-V
breakdown
voltage)
Note Pull-up resistor operated only when executing input instructions
(when pins are low level, current flows from VDD to pins).
11
11 Page | ||
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| PDF Descargar | [ Datasheet UPD75P3018GK-BE9.PDF ] | |
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