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PDF UPD75P108BGF-3BE Data sheet ( Hoja de datos )
| Número de pieza | UPD75P108BGF-3BE | |
| Descripción | 4-BIT SINGLE-CHIP MICROCOMPUTER | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75P108B
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The µPD75P108B is a version of the µPD75108 in which the on-chip mask ROM is replaced by one-time
PROM which can be written to once only, or EPROM which is capable of program write, erasure and rewrite.
Also, since the µPD75P108B is capable of program write by a user, it can easily be exchanged with the mask
version, allowing evaluation at low voltage.
Detailed functional descriptions are shown in the following User’s Manual. Be sure to read for designations.
µPD751×× Series User’s Manual : IEM-922
FEATURES
• Version with on-chip PROM, allowing low-voltage operation VDD = 2.7 to 6.0 V
• µPD75108 compatible
• Memory capacity
• Program memory (PROM) : 8064 × 8 bits
• Data memory (RAM)
: 512 × 4 bits
• Correspondence to QTOP™ microcomputer
ORDERING INFORMATION
Ordering Code
Package
On-Chip ROM
µPD75P108BCW
µPD75P108BDW
µPD75P108BGF-3BE
64-pin plastic shrink DIP (750 mil)
64-pin ceramic shrink DIP (with window)
64-pin plastic QFP (14 × 20 mm, 1.0 mm pitch)
One-time PROM
EPROM
One-time PROM
Note There is no on-chip pull-up resistor function by means of a mask option.
5
QUALITY GRADE
Standard
Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
In this ducument, common parts of one-time PROM products and EPROM products are represented as
PROM.
The information in this document is subject to change without notice.
Document No. IC-2580C
(O. D. No. IC-7987C)
Date Published December 1993 P
Printed in Japan
The mark 5 shows major revised points.
© NEC Corporation 1989
1 page  
TI0
PTO0/P20
TI1
PTO1/P21
SI/P03
SO/P02
SCK/P01
BASIC
INTERVAL
TIMER
INTBT
TIMER/EVENT
COUNTER
#0
INTT0
TIMER/EVENT
COUNTER
#1
INTT1
SERIAL
INTERFACE
INTSIO
INT0/P10
INT1/P11
INT2/P12
INT3/P13
INT4/P00
INTER-
RUPT
CONTROL
PTH00-PTH03 4
PROGRAM-
MABLE
THRESHOLD
PORT #0
PROGRAM
COUNTER (13)
ROM
PROGRAM
MEMORY
8064 × 8 BITS
ALU
SP(8)
CY
BANK
DECODE
AND
CONTROL
GENERAL REG.
RAM DATA
MEMORY
512 × 4 BITS
fXX / 2N
CLOCK
OUTPUT
CONTROL
CLOCK
DIVIDER
CLOCK
GENERATOR
STAND BY
CONTROL
CPU CLOCK
Φ
PCL/P22
X1 X2
VPP VDD VSS RESET
BIT SEQ.
BUFFER
(16)
PORT 0 4 P00-P03
PORT 1 4 P10-P13
PORT 2 4 P20-P23
PORT 3
4
P30-P33
/MD0-MD3
PORT 4 4 P40-P43
PORT 5 4 P50-P53
PORT 6 4 P60-P63
PORT 7 4 P70-P73
PORT 8 4 P80-P83
PORT 9 4 P90-P93
PORT 12 4 P120-P123
PORT 13 4 P130-P133
PORT 14 4 P140-P143
5 Page 
(7) Type N
Comparator
IN
+
–
VREF (Threshold Voltage)
1.4 RECOMMENDED CONNECTION OF UNUSED PINS
Pin
PTH00 to PTH03
TI0
TI1
P00
P01 to P03
P10 to P13
P20 to P23
P30 to P33
P40 to P43
P50 to P53
P60 to P63
P70 to P73
P80 to P83
P90 to P93
P120 to P123
P130 to P133
P140 to P143
RESET
Recommended Connection
Connect to VSS or VDD.
Connect to VSS.
Connect to VSS or VDD.
Connect to VSS.
Input status : Connect to VSS or VDD.
Output status : Leave open.
Connect to VDD.
µPD75P108B
11
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