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UPD75P068GB-3B4 の電気的特性と機能

UPD75P068GB-3B4のメーカーはNECです、この部品の機能は「4 BIT SINGLE-CHIP MICROCOMPUTER」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD75P068GB-3B4
部品説明 4 BIT SINGLE-CHIP MICROCOMPUTER
メーカ NEC
ロゴ NEC ロゴ 




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UPD75P068GB-3B4 Datasheet, UPD75P068GB-3B4 PDF,ピン配置, 機能
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75P068
4 BIT SINGLE-CHIP MICROCOMPUTER
The µPD75P068 is produced by replacing the internal mask ROM of the µPD75068 with a one-time PROM
in which data can be written once.
The following user's manual describes the details of the functions of the µPD75P068. Be sure to read it
before designing an application system.
µPD75068 User's Manual: IEU-1366
FEATURES
Compatible with the µPD75068
• Can be replaced with the µPD75068 containing mask ROM on a full-production basis.
Internal one-time PROM: 8064 words × 8 bits
Internal RAM: 512 words × 4 bits
Internal pull-up resistors can be specified with software: Ports 0 to 3 and 6
N-ch open-drain input-output: Ports 4 and 5
Can operate at low voltage: VDD = 2.7 to 6.0 V
ORDERING INFORMATION
Part number
µPD75P068CU
µPD75P068GB-3B4
Package
42-pin plastic shrink DIP (600 mil)
44-pin plastic QFP (Square 10 mm)
Quality grade
Standard
Standard
Caution The µPD75P068 is not provided with mask-selected pull-up resistors.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
Document No. IC-3290A
(O.D. No. IC-8623A
Date Published April 1994 P
Printed in Japan
The information in this document is subject to change without notice.
Major changes in this revision are indicated by stars (5) in the margins.
© NEC CORPORATIO1N9910993

1 Page





UPD75P068GB-3B4 pdf, ピン配列
TI0/P13
PTO0/P20
SI/SB1/P03
SO/SB0/P02
SCK/P01
Basic interval
timer
INTBT
Timer/
counter #0
INTT0
Serial
interface
INTCSI
INT0/P10
INT1/P11
INT2/P12
INT4/P00
KR0-KR3/P60-P63 4
Interrupt
control
BUZ/P23
Watch timer
INTW
AVREF
AVSS
AN0-AN3/P110-P113
AN4-AN7/P60-P63
8
A/D
converter
Program
counter (13)
SP
ALU CY
Bank
PROM program
memory
8064 × 8 bits
Decode and
control
General register
RAM data
memory
512 × 4 bits
Bit sequential
buffer
Port 0 4 P00-P03
Port 1 4 P10-P13
Port 2 4 P20-P23
Port 3 4 P30/MD0-P33/MD3
Port 4 4 P40-P43
Port 5 4 P50-P53
Port 6 4 P60-P63
Port 11 4 P110-P113
fX/2N
Clock output
control
Clock
divider
Clock generator
Sub Main
CPU clock
Φ
Stand by control
PCL/P22
XT1 XT2 X1 X2
VPP VDD VSS RESET


3Pages


UPD75P068GB-3B4 電子部品, 半導体
µPD75P068
1.2 NON-PORT PINS
Pin
TI0
PTO0
PCL
BUZ
SCK
SO/SB0
SI/SB1
INT4
INT0
INT1
INT2
KR0-KR3
AN0-AN3
AN4-AN7
AVREF
AVSS
X1, X2
XT1, XT2
RESET
MD0-MD3
VPPNote 2
VDD
VSS
Input/
output
Input
I/O
I/O
I/O
I/O
I/O
I/O
Input
Input
Input
I/O
Input
I/O
Input
Input
Input
Input
I/O
Shared pin
P13
P20
P22
P23
P01
P02
P03
P00
P10
P11
P12
P60-P63/
AN4-AN7
P110-P113
P60-P63/
KR0-KR3
P30-P33
Function
Input for receiving external event pulse signal for
timer/event counter
Timer/event counter output
Clock output
Output for arbitrary frequency output (for buzzer
output or system clock trimming)
Serial clock I/O
Serial data output
Serial bus I/O
Serial data input
Serial bus I/O
Edge detection vectored interrupt input (either
rising edge or falling edge detection)
Edge detection vectored interrupt input (detection
edge selectable)
Edge detection testable input (rising edge
detection)
Parallel falling edge detection testable input
For A/D converter only
8-bit analog input
Reference voltage input
GND potential
Crystal/ceramic connection for main system clock
generation. When external clock signal is used, it
is applied to X1, and its reverse phase signal is
applied to X2.
Crystal connection for subsystem clock generation.
When external clock signal is used, it is applied to
XT1, and its reverse phase signal is applied to
XT2. XT1 can be used as a 1-bit input (test).
System reset input
Mode selection when writing to or verifying
program memory (PROM)
Programming voltage application when writing to
or verifying program memory (PROM)
Directly connected to VDD during normal operation.
+12.5 V is applied when data is written in PROM or
when the PROM is verified.
Main power supply
GND potential
I/O
When reset circuit
typeNote 1
Input
Input
Input
Input
Input
Input
B -C
E-B
E-B
E-B
F -A
F -B
Input
M -C
Input
B
Input
B -C
Input
Input
B -C
Y -D
Y-A
Y -D
Z
Z
——
Input
B
E-B
——
——
——
Notes 1. The circle (q) indicates the Schmitt trigger input.
2. Unless the VPP pin is directly connected to the VDD pin during normal operation, the
µPD75P068 does not operate normally.
6

6 Page



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部品番号部品説明メーカ
UPD75P068GB-3B4

4 BIT SINGLE-CHIP MICROCOMPUTER

NEC
NEC


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