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UPD75P0076GT の電気的特性と機能

UPD75P0076GTのメーカーはNECです、この部品の機能は「4-BIT SINGLE-CHIP MICROCONTROLLER」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD75P0076GT
部品説明 4-BIT SINGLE-CHIP MICROCONTROLLER
メーカ NEC
ロゴ NEC ロゴ 




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UPD75P0076GT Datasheet, UPD75P0076GT PDF,ピン配置, 機能
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75P0076
4-BIT SINGLE-CHIP MICROCONTROLLER
The µPD75P0076 replaces the µPD750068’s internal mask ROM with a one-time PROM and features expanded ROM
capacity.
Because the µPD75P0076 supports programming by users, it is suitable for use in prototype testing for system
development using the µPD750064, 750066, and 750068 products, and for use in small-lot production.
Detailed information about function is provided in the following user’s manual.
Be sure to read it before designing:
µPD750068 User’s Manual: U10670E
FEATURES
Compatible with µPD750068
Memory capacity:
• PROM : 16384 x 8 bits
• RAM : 512 x 4 bits
Can operate with same power supply voltage as the mask ROM version µPD750068
VDD = 1.8 to 5.5 V
On-chip A/D converter capable of low-voltage operation (AVREF = 1.8 to 5.5 V)
8-bit resolution x 8 channels
Small shrink SOP package
ORDERING INFORMATION
Part Number
µPD75P0076CU
µPD75P0076GT
Package
42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)
Caution On-chip pull-up resistors by mask option cannot be provided.
The information in this document is subject to change without notice.
Document No. U10232EJ1V0DS00 (1st edition)
Date Published December 1996 N
Printed in Japan
The mark shows major revised points.
©
1995

1 Page





UPD75P0076GT pdf, ピン配列
µPD75P0076
CONTENTS
1. PIN CONFIGURATION (Top View) ................................................................................................... 4
2. BLOCK DIAGRAM ............................................................................................................................ 5
3. PIN FUNCTIONS ............................................................................................................................... 6
3.1 Port Pins ................................................................................................................................................... 6
3.2 Non-port Pins ........................................................................................................................................... 7
3.3 Equivalent Circuits for Pins .................................................................................................................... 9
3.4 Handling of Unused Pins ......................................................................................................................... 12
4. SWITCHING BETWEEN Mk I AND Mk II MODES ............................................................................ 13
4.1 Difference betweens Mk I Mode and Mk II Mode .................................................................................... 13
4.2 Setting of Stack Bank Selection (SBS) Register .................................................................................... 14
5. DIFFERENCES BETWEEN µPD75P0076 AND µPD750064, 750066 AND 750068 ........................ 15
6. MEMORY CONFIGURATION ............................................................................................................ 16
7. INSTRUCTION SET ........................................................................................................................... 18
8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY .................................................... 29
8.1 Operation Modes for Program Memory Write/Verify ............................................................................. 29
8.2 Steps in Program Memory Write Operation ............................................................................................ 30
8.3 Steps in Program Memory Read Operation ............................................................................................ 31
8.4 One-time PROM Screening ..................................................................................................................... 32
9. ELECTRICAL SPECIFICATIONS...................................................................................................... 33
10. CHARACTERISTICS CURVES (REFERENCE VALUES) ................................................................ 49
11. PACKAGE DRAWINGS .................................................................................................................... 51
12. RECOMMENDED SOLDERING CONDITIONS ................................................................................. 53
APPENDIX A DIFFERENCES AMONG µPD75068, 750068 AND 75P0076 ......................................... 54
APPENDIX B DEVELOPMENT TOOLS ................................................................................................. 55
APPENDIX C RELATED DOCUMENTS ................................................................................................. 58
3


3Pages


UPD75P0076GT 電子部品, 半導体
µPD75P0076
3. PIN FUNCTIONS
3.1 Port Pins
Pin name
P00
P01
I/O Alternate function
Function
I INT4
I/O SCK
This is a 4-bit input port (PORT0).
For P01 to P03, on-chip pull-up resistors are
software-specifiable in 3-bit units.
8-bit
accessible
Not
available
After
reset
Input
I/O circuit
typeNote 1
<B>
<F>-A
P02 I/O SO/SB0
<F>-B
P03 I/O SI/SB1
<M>-C
P10
I INT0
This is a 4-bit input port (PORT1).
Not
Input
<B>-C
Connections of on-chip pull-up resistors are
available
P11
INT1
software-specifiable in 4-bit units. P10/INT0
can select a noise elimination circuit.
P12 TI1/INT2
P13 TI0
P20 I/O PTO0 This is a 4-bit I/O port (PORT2).
Not
Input
E-B
Connections of on-chip pull-up resistors are
available
P21
PTO1
software-specifiable in 4-bit units.
P22 PCL
P23 BUZ
P30 I/O MD0
P31 MD1
P32 MD2
This is a programmable 4-bit I/O port (PORT3).
Input and output can be specified in single-bit
units. Connections of on-chip pull-up resistors
are software-specifiable in 4-bit units.
Not
available
Input
E-B
P33 MD3
P40Note 2
P41Note 2
P42Note 2
I/O D0
D1
D2
This is an N-ch open-drain 4-bit I/O port
(PORT4). In the open-drain mode, withstands
up to 13 V. Also used as data I/O pin
(lower 4 bits) for program memory (PROM)
write/verify.
Available
High
impedance
M-E
P43Note 2
D3
P50Note 2
P51Note 2
P52Note 2
I/O D4
D5
D6
This is an N-ch open-drain 4-bit I/O port
(PORT5). In the open-drain mode, withstands
up to 13 V. Also used as data I/O pin
(upper 4 bits) for program memory (PROM)
write/verify.
High
impedance
M-E
P53Note 2
D7
P60
I/O KR0/AN4
This is a programmable 4-bit I/O port (PORT6).
Not
Input
<Y>-D
Input and output can be specified in single-bit available
P61
KR1/AN5
units. Connections of on-chip pull-up resistors
are software-specifiable in 4-bit units.
P62 KR2/AN6
P63 KR3/AN7
P110
P111
I AN0
AN1
This is a 4-bit input port (PORT11).
Not
available
Input
Y-A
P112
AN2
P113
AN3
Notes 1. Circuit types enclosed in brackets indicate Schmitt triggered inputs.
2. Low-level input current leakage increases when input instructions or bit manipulation instructions are executed.
6

6 Page



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部品番号部品説明メーカ
UPD75P0076GT

4-BIT SINGLE-CHIP MICROCONTROLLER

NEC
NEC


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