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UPD72874GC-YEB の電気的特性と機能

UPD72874GC-YEBのメーカーはNECです、この部品の機能は「IEEE1394 OHCI 1.1 COMPLIANT 3PORT PHY-LINK 1-CHIP HOST CONTROLLER」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD72874GC-YEB
部品説明 IEEE1394 OHCI 1.1 COMPLIANT 3PORT PHY-LINK 1-CHIP HOST CONTROLLER
メーカ NEC
ロゴ NEC ロゴ 




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UPD72874GC-YEB Datasheet, UPD72874GC-YEB PDF,ピン配置, 機能
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µPD72874
IEEE1394 OHCI 1.1 COMPLIANT 3PORT PHY-LINK 1-CHIP HOST CONTROLLER
The µPD72874 is the LSI that integrated OHCI-Link and PHY function into a single chip. The µPD72874 complies
with the 1394 OHCI Specification 1.1 and the IEEE Std 1394a-2000 specifications, and works up to 400 Mbps.
It makes design so compact for PC and PC card application.
FEATURES
• Compliant with Link Layer Services as defined in 1394 Open Host Controller Interface specification release 1.1
• Compliant with Physical Layer Services as defined in IEEE Std 1394a-2000
• Provides three cable ports at 100/200/400 Mbps
• Super Low power consumption for Physical Layer
• Compliant with protocol enhancement as defined in IEEE Std1394a-2000
• Modular 32-bit host interface compliant to PCI Specification release 2.2
• Supports PCI-Bus Power Management Interface Specification release 1.1
• Modular 32-bit host interface compliant to Card Bus Specification
• Cycle Master and Isochronous Resource Manager capable
Built-in FIFOs for isochronous transmit (2048 bytes), asynchronous transmit (2048 bytes), and receive (3072
bytes)
• Supports D0, D1, D2, D3hot
• Supports wake up function from D3cold
• 32-bit CRC generation and checking for receive/transmit packets
• 4 isochronous transmit DMAs and 4 isochronous receive DMAs supported
• 32-bit DMA channels for physical memory read/write
• Clock generation by 24.576 MHz X’tal
• 2-wire Serial EEPROM TM interface supported
• Separate power supply Link and PHY
• Programmable latency timer from serial EEPROM in Cardbus mode (CARD_ON = 1)
ORDERING INFORMATION
Part number
µPD72874GC-YEB
Package
120-pin plastic TQFP (Fine pitch) (14 x 14)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S15306EJ2V0DS00 (2nd edition)
Date Published April 2002 NS CP (K)
Printed in Japan
The mark shows major revised points.
2001

1 Page





UPD72874GC-YEB pdf, ピン配列
BLOCK DIAGRAMS
P_AVDD
PC0
PC1
PC2
P_DVDD
GND
GND
µPD72874
P_RESET
CPS
GROM_EN
GROM_SCL
GROM_SDA
PCI_VDD
L_VDD
Preliminary Data Sheet S15306EJ2V0DS
3


3Pages


UPD72874GC-YEB 電子部品, 半導体
µPD72874
CONTENTS
1. PIN FUNCTIONS..................................................................................................................................... 8
1.1 PCI/Cardbus Interface Signals: (52 pins) ...................................................................................... 8
1.2 PHY Signals: (20 pins) .................................................................................................................. 10
1.3 PHY Control Signals: (4 pins)....................................................................................................... 10
1.4 PCI/Cardbus Select Signal: (1 pin)............................................................................................... 10
1.5 Serial ROM Interface Signals: (3 pins)......................................................................................... 11
1.6 D3cold Wake Up Function Signals: (2 pins) ............................................................................... 11
1.7 IC: (7 pins) ...................................................................................................................................... 11
1.8 VDD................................................................................................................................................... 12
1.9 GND................................................................................................................................................. 12
2. PHY REGISTERS................................................................................................................................... 13
2.1 Complete Structure for PHY Registers........................................................................................ 13
2.2 Port Status Page (Page 000)......................................................................................................... 16
2.3 Vendor ID Page (Page 001) ........................................................................................................... 17
2.4 Vendor Dependent Page (Page 111 : Port_select 0001) ............................................................ 17
3. CONFIGURATION REGISTERS .......................................................................................................... 18
3.1 PCI Bus Mode Configuration Register (CARD_ON = Low)........................................................ 18
3.1.1 Offset_00 Vendor ID Register ........................................................................................................... 19
3.1.2 Offset_02 Device ID Register............................................................................................................ 19
3.1.3 Offset_04 Command Register ........................................................................................................... 19
3.1.4 Offset_06 Status Register ................................................................................................................. 20
3.1.5 Offset_08 Revision ID Register ......................................................................................................... 21
3.1.6 Offset_09 Class Code Register......................................................................................................... 21
3.1.7 Offset_0C Cache Line Size Register................................................................................................. 21
3.1.8 Offset_0D Latency Timer Register .................................................................................................... 21
3.1.9 Offset_0E Header Type Register ...................................................................................................... 21
3.1.10 Offset_0F BIST Register .................................................................................................................. 21
3.1.11 Offset_10 Base Address 0 Register ................................................................................................ 22
3.1.12 Offset_2C Subsystem Vendor ID Register ...................................................................................... 22
3.1.13 Offset_2E Subsystem ID Register................................................................................................... 22
3.1.14 Offset_34 Cap_Ptr Register ............................................................................................................ 22
3.1.15 Offset_3C Interrupt Line Register.................................................................................................... 22
3.1.16 Offset_3D Interrupt Pin Register ..................................................................................................... 23
3.1.17 Offset_3E Min_Gnt Register ........................................................................................................... 23
3.1.18 Offset_3F Max_Lat Register ........................................................................................................... 23
3.1.19 Offset_40 PCI_OHCI_Control Register ........................................................................................... 23
3.1.20 Offset_60 Cap_ID & Next_Item_Ptr Register .................................................................................. 23
3.1.21 Offset_62 Power Management Capabilities Register...................................................................... 24
3.1.22 Offset_64 Power Management Control/Status Register.................................................................. 25
3.2 CardBus Mode Configuration Register (CARD_ON = High)...................................................... 26
3.2.1 Offset_14/18 Base Address 1/2 Register (Cardbus Status Registers).............................................. 27
3.2.2 Offset_28 Cardbus CIS Pointer......................................................................................................... 28
3.2.3 Offset_80 CIS Area ........................................................................................................................... 28
6 Preliminary Data Sheet S15306EJ2V0DS

6 Page



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部品番号部品説明メーカ
UPD72874GC-YEB

IEEE1394 OHCI 1.1 COMPLIANT 3PORT PHY-LINK 1-CHIP HOST CONTROLLER

NEC
NEC


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