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UPD72862GC-9EU の電気的特性と機能

UPD72862GC-9EUのメーカーはNECです、この部品の機能は「IEEE1394 OHCI HOST CONTROLLER」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD72862GC-9EU
部品説明 IEEE1394 OHCI HOST CONTROLLER
メーカ NEC
ロゴ NEC ロゴ 




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UPD72862GC-9EU Datasheet, UPD72862GC-9EU PDF,ピン配置, 機能
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD72862
IEEE1394 OHCI HOST CONTROLLER
The µPD72862 is IEEE1394 OHCI-Link controller. The µPD72862 complies with the P1394a draft 2.0
specifications and works up to 400 Mbps.
It supports both of the Cardbus interface and the PCI bus interface.
FEATURES
• Compliant with Link Layer Services as defined in 1394 Open Host Controller Interface specification release 1.0
• Compliant with protocol enhancement as defined in P1394a draft 2.0
• Modular 32-bit host interface compliant to PCI Specification release 2.1
• Supports PCI-Bus Power Management Interface Specification release 1.0
• Supports Cardbus
• Equipped CIS register
• Cycle Master and Isochronous Resource Manager capable
• Compatible to PHY Layer implementation of 100/200/400 Mbps via 2/4/8-bit data interface
• Built-in FIFOs for isochronous transmit (1024 bytes), asynchronous transmit (1024 bytes), and receive (2048
bytes)
• 32-bit CRC generation and checking for receive/transmit packets
• 4-isochronous transmit DMAs and 4-isochronous receive DMAs supported
• Support both IEEE1394-1995 compliant PHY and P1394a compliant PHY
• Internal control and operational registers direct-mapped to PCI configuration space
• 2-wire Serial EEPROMTM interface supported
ORDERING INFORMATION
Part number
Package
µPD72862GC-9EU
100-pin plastic TQFP (Fine pitch) (14 x 14)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14265EJ2V0DS00 (2nd edition)
Date Published December 1999 NS CP (K)
Printed in Japan
The mark 5 shows major revised points.
1999

1 Page





UPD72862GC-9EU pdf, ピン配列
µPD72862
BLOCK DIAGRAM
Serial ROM Interface
PCI Controller Interface
(Master, Parity Check & Generator) PCI-DMA IOREG
CSR
(CIS)
PFCOMM
Buf
Byte
Swap
OPCI Internal Bus
PCIS_CNT
PCIS Bus (PCI Slave Bus)
PCICFG
ATDMA
PAU
OPCIBUS_ARB
GRSU
GRQU
ITDMA
IRDMA0-
IRDMA3
SFIDU
Byte
Swap
ATF
Byte
Swap
ITF
ITCF
RF
Byte
Swap
RCF
Link Layer
Core
IOREG
ATDMA
ATF
CIS
CSR
IOREG
IRDMA
ITCF
ITDMA
ITF
OPCIBUS_ARB
PAU
PCICFG
PCIS_CNT
PFCOMM
RCF
RF
SFIDU
: Asynchronous Transmit DMA
: Asynchronous Transmit FIFO
: CIS Register
: Control and Status Registers
: IO Registers
: Isochronous Receive DMA
: Isochronous Transmit Control FIFO
: Isochronous Transmit DMA
: Isochronous Transmit FIFO
: OPCI Internal Bus Arbitration
: Physical Response and Request Unit
: PCI Configuration Registers
: PHY Control Isochronous Control
: Pre Fetch Command FIFO
: Receive Control FIFO
: Receive FIFO
: Self-ID DMA
Data Sheet S14265EJ2V0DS00
3


3Pages


UPD72862GC-9EU 電子部品, 半導体
µPD72862
CONTENTS
1. PIN FUNCTIONS ..................................................................................................................................... 8
1.1 PCI Bus Interface Signals: (52 pins) .............................................................................................. 8
1.2 PCI/Cardbus Select Signals: (2 pins) ............................................................................................. 9
1.3 PHY/Link Interface Signals: (15 pins) .......................................................................................... 10
1.4 Serial ROM Interface Signals: (3 pins) ......................................................................................... 10
1.5 Miscellaneous Signal: (1 pin) ....................................................................................................... 10
1.6 IC: (3 pins) ...................................................................................................................................... 10
1.7 NC: (5 pins)..................................................................................................................................... 10
1.8 VDD: (8 pins) .................................................................................................................................... 10
1.9 VSS: (11 pins) .................................................................................................................................. 10
2. REGISTER DESCRIPTIONS................................................................................................................. 11
2.1 PCI Bus Mode Configuration Register ( CARD_ON=Low ) ........................................................ 11
2.1.1 Offset_00 VendorID Register .............................................................................................................12
2.1.2 Offset_02 DeviceID Register..............................................................................................................12
2.1.3 Offset_04 Command Register............................................................................................................12
2.1.4 Offset_06 Status Register ..................................................................................................................13
2.1.5 Offset_08 Revision ID Register ..........................................................................................................14
2.1.6 Offset_09 Class Code Register..........................................................................................................14
2.1.7 Offset_0C Cache Line Size Register..................................................................................................14
2.1.8 Offset_0D Latency Timer Register .....................................................................................................14
2.1.9 Offset_0E Header Type Register .......................................................................................................14
2.1.10 Offset_0F BIST Register ...................................................................................................................14
2.1.11 Offset_10 Base Address 0 Register .................................................................................................15
2.1.12 Offset_2C Subsystem Vendor ID Register.......................................................................................15
2.1.13 Offset_2E Subsystem ID Register....................................................................................................15
2.1.14 Offset_30 Expansion Rom Base Address Register..........................................................................15
2.1.15 Offset_34 Cap_Ptr Register .............................................................................................................15
2.1.16 Offset_3C Interrupt Line Register.....................................................................................................16
2.1.17 Offset_3D Interrupt Pin Register ......................................................................................................16
2.1.18 Offset_3E Min_Grant Register .........................................................................................................16
2.1.19 Offset_3F Max Lat Register .............................................................................................................16
2.1.20 Offset_40 PCI_OHCI_Control Register ............................................................................................16
2.1.21 Offset_60 Cap_ID & Next_Item_Ptr Register ...................................................................................17
2.1.22 Offset_62 Power Management Capabilities Register.......................................................................17
2.1.23 Offset_64 Power Management Control/Status Register...................................................................17
2.2 CardBus Mode Configuration Register ( CARD_ON=High ) ...................................................... 18
2.2.1 Offset_14/18 Base_Address_1/2 Register (CardBus Status Registers) ............................................19
2.2.2 Offset_28 Cardbus CIS Pointer..........................................................................................................20
2.2.3 Offset_80 CIS Area ............................................................................................................................20
3. SERIAL ROM INTERFACE.................................................................................................................. 21
3.1 Serial EEPROM Register ............................................................................................................... 21
3.2 Serial EEPROM Register Description .......................................................................................... 21
3.3 Load Control................................................................................................................................... 25
3.4 Programming Sequence Example................................................................................................ 25
6 Data Sheet S14265EJ2V0DS00

6 Page



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部品番号部品説明メーカ
UPD72862GC-9EU

IEEE1394 OHCI HOST CONTROLLER

NEC
NEC


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